Nonvolatile ferroelectric random access memory device and a method of reading data thereof

• US 6,236,588 B1
• Filed: 04/10/2000
• Issued: 05/22/2001
• Est. Priority Date: 07/28/1999
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Koo, Bon-Jae
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/546,552
• Time in Patent Office: 407 Days
• Field of Search: 365/210, 365/145, 365/149, 365/205, 365/207, 365/208
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A ferroelectric random access memory device is disclosed, which comprises a bit line, a reference bit line, a memory cell, a sense amplifier, and a voltage-supplying circuit. The reference bit line corresponds to the first bit line and has a reference voltage; the memory cell is coupled to the bit line; the sense amplifier operates to sense a voltage difference between the bit line and the reference bit line; and the voltage-supplying circuit operates to supply the bit line and the reference bit line with the same amount of charge before the sense amplifier is activated. According to the present invention, a voltage induced on a bit line during a sensing operation can be maintained at a high level regardless of the an increase in the degree of integration on the ferroelectric random access memory.

Claims

1. A random access memory device comprising:

a top bit line;

a top memory cell coupled to the top bit line;

a bottom bit line corresponding to the top bit line;

a sense amplifier coupled to the top and bottom bit lines, for sensing a voltage difference between the top and bottom bit lines; and

a circuit for increasing a voltage of the top and bottom bit lines, before the sense amplifier is activated.

2. A random access memory device, as recited in claim 1, wherein the top memory cell comprises a ferroelectric capacitor.

3. A random access memory device, as recited in claim 1, wherein the circuit for increasing a voltage comprises:

a first capacitor having a first electrode coupled to a first plate line;

a first transistor having a first current path formed between the top bit line and a second electrode of the first capacitor, and a gate coupled to a first word line;

a second capacitor having a first electrode coupled to a second plate line; and

a second transistor having a current path formed between the bottom bit line and a second electrode of the second capacitor, and a gate coupled to a second word line.

4. A random access memory device, as recited in claim 3, wherein the first and second capacitors each comprise a capacitor selected from the group of a ferroelectric capacitor and a linear capacitor.

5. A random access memory device, as recited in claim 4, wherein when the first and second capacitors comprise ferroelectric capacitors, a pulse signal is simultaneously applied to the second electrodes of the first and second capacitors through corresponding first and second NMOS transistors after an inactivation of the first and second word lines, so that the first and second capacitors are polarized to an initial domain.

6. A random access memory device, as recited in claim 3, wherein the first and second word lines are simultaneously activated during a sensing operation.

7. A random access memory device, as recited in claim 6, wherein the first and second plate lines are simultaneously activated during an activation of the first and second word lines.

8. A random access memory device, as recited in claim 1, further comprising

a bottom reference cell that is coupled to the bottom bit line and which provides the bottom bit line with a reference voltage.

9. A random access memory device, as recited in claim 8, further comprising:

a bottom memory cell coupled to the bottom bit line; and

a top reference cell that is coupled to the top bit line and which provides the top bit line with a reference voltage,

wherein when the top memory cell and the bottom reference cell are activated, the bottom memory cell and the top reference cell are deactivated, and

wherein when the bottom memory cell and the top reference cell are activated, the top memory cell and the bottom reference cell are deactivated.

10. A random access memory device comprising:

a top memory cell array having a plurality of top word lines, a plurality of top bit lines, and a plurality of top memory cells arranged in a matrix form between the top word lines and the top bit lines;

a plurality of bottom bit lines corresponding to the top bit lines;

a bottom reference cell array having a plurality of bottom reference cells commonly coupled to a bottom reference word line, for generating first reference voltages to be supplied into the bottom bit lines;

a row decoder circuit for selecting a top word line related to a memory cell to be selected and the bottom reference word line in response to address signals;

a sense amplifier circuit connected to the top and bottom bit lines, for sensing a voltage difference between corresponding top and bottom bit lines; and

a charge dumping circuit for supplying the top and bottom bit lines with the same amount of charge before the sense amplifier circuit performs a sensing operation.

11. A random access memory device, as recited in claim 10, further comprising

a bottom memory cell array connected to the bottom bit lines and having a plurality of bottom word lines and a plurality of bottom memory cells arranged in a matrix form between the bottom word lines and the bottom bit lines; and

a top reference cell array connected to the top bit lines and having a plurality of top reference cells commonly coupled to a top reference word line, for generating second reference voltages to be supplied into the top bit lines, respectively.

12. A random access memory device, as recited in claim 11, wherein the top and bottom memory cells and the top and bottom reference cells each comprise a ferroelectric capacitor.

13. A random access memory device, as recited in claim 11, wherein the charge dumping circuit comprises a first charge dumping portion coupled to the first bit lines and a second charge dumping portion coupled to the second bit lines.

14. A random access memory device, as recited in claim 12,

wherein the first charge dumping portion comprises a plurality of first capacitors and a first plurality of access transistors, corresponding to the plurality of first bit lines,

wherein each of the first capacitors has a first electrode coupled to a first plate line, and

wherein each of the first access transistors has a current path formed between a corresponding first bit line and a second electrode of a corresponding first capacitor, and has a gate coupled to a third word line.

15. A random access memory device, as recited in claim 13,

wherein the second charge dumping portion comprises a plurality of second capacitors and a plurality of second access transistors, corresponding to the second bit lines,

wherein each of the second capacitors has a first electrode coupled to a second plate line, and

wherein each of the second access transistors has a current path formed between a corresponding second bit line and a second electrode of a corresponding second capacitor, and has a gate coupled to a fourth word line.

16. A random access memory device, as recited in claim 15,

wherein each of the first and second capacitors comprises a ferroelectric capacitor, and

wherein a pulse signal is simultaneously applied to the second electrodes of the first and second capacitors through corresponding first and second NMOS transistors so that the first and second capacitors are polarized to an initial domain after an inactivation of the third and fourth word lines.

17. A random access memory device, as recited in claim 11,

wherein when the top memory cell array and the bottom reference cell array are activated, the bottom memory cell array and the top reference cell array are deactivated, and

wherein when the bottom memory cell array and the top reference cell array are activated, the top memory cell array and the bottom reference cell array are deactivated.