Method for simultaneously programming plural flash memories having invalid blocks

• US 6,236,593 B1
• Filed: 04/26/2000
• Issued: 05/22/2001
• Est. Priority Date: 04/27/1999
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Choi, Young-Jun, Hong, Sung-In
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/558,561
• Time in Patent Office: 391 Days
• Field of Search: 365/185.11, 365/230.03, 711/103
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

Disclosed is a method for programming flash memories, each of which has a memory cell array divided into plural blocks. Each of the blocks is associated with block status information indicating whether it is valid. According to the programming method of the present invention, first, a parallel-programming process is performed for valid blocks of all of the flash memories. Then, a serial-programming process is performed for flash memories having invalid blocks. This enables the time required for programming flash memories with one or more invalid blocks to be reduced.

Claims

1. A method for programming a plurality of electrically programmable nonvolatile memory devices each having a memory cell array divided into plural blocks of memory cells, wherein each of the blocks stores block status information indicating whether it is valid or not, the method comprising the steps of:

(a) reading the block status information from each memory device and storing the block status information in a data storage unit;

(b) dividing the plural blocks of each memory device into first, second and third storage regions in accordance with the stored block status information and designating a first location of each second storage region;

(c) selecting blocks, at the designated location, of the second storage regions of the respective memory devices;

(d) after selecting memory devices having the selected blocks which are valid, simultaneously programming the selected valid blocks of the selected memory devices;

(e) designating a next location of each memory device when the selected blocks are not the last blocks of the respective second storage regions; and

(f) performing the steps (c) through (e) repeatedly until the selected blocks are determined to be the last blocks of the respective second storage regions.

2. The method according to claim 1, further comprising the steps of:

(g) selecting one of the memory devices with at least one invalid block;

(h) programming at least one block of the third storage region of the selected memory device instead of the at least one invalid block thereof;

(i) programming the stored block status information of the selected memory device in the first storage region of the selected memory device;

(j) selecting a next memory device when the selected device is not last; and

(k) performing the steps (h) through (j) until the selected device is determined to be a last memory device.

3. The method according to claim 1, wherein the data storage unit is a random access memory installed in a system for controlling the programming for plural memory devices.

4. A method for programming electrically programmable nonvolatile memory devices sharing data and address buses, under the control of a system which comprises a central processing unit, an interface unit, a RAM unit, and a ROM unit, wherein each memory device has a memory cell array divided into plural blocks of memory cells, and wherein each of the blocks stores block status information indicating whether it is valid or not, the method comprising the steps of:

(a) reading the block status information from each memory device and storing the block status information in the RAM unit;

(b) dividing the plural blocks of each memory device into first, second and third storage regions in accordance with the stored block status information and designating a first location of each memory device;

(c) selecting blocks, at the designated location, of the second storage regions of the respective memory devices;

(d) after selecting memory devices having the selected blocks which are valid, simultaneously programming the selected valid blocks of the selected memory devices;

(e) checking whether the selected blocks are the last blocks of the respective second storage regions;

(f) designating a next location of each memory device when the selected blocks are not last;

(g) performing the steps (c) through (f) repeatedly until the selected blocks are determined to be the last blocks of the respective second storage regions; and

(h) sequentially programming the memory devices having one or more invalid blocks.

5. The method according to claim 4, whererin the step (h) comprises the steps of:

(i) selecting one of the memory devices with at least one invalid block;

(j) programming at least one block of the third storage region of the selected memory device instead of the at least one invalid block thereof;

(k) programming the stored block status information, as the file allocation table data, of the selected memory device in the first storage region of the selected memory device;

(l) selecting a next memory device when the selected device is not last; and

(m) performing the steps (j) through (l) until the selected device is determined to be a last memory device.

6. A method for programming a plurality of flash memory devices each having a memory cell array divided into plural blocks of memory cells, wherein each of the blocks stores block status information indicating whether it is valid or not, the method comprising the steps of:

(a) reading the block status information from each flash memory device and storing the block status information in a data storage unit;

(b) dividing the plural blocks of each flash memory device into first, second and third storage regions in accordance with the stored block status information and designating a first location of each second storage region;

(c) selecting blocks, at the designated location, of the second storage regions of the respective memory devices;

(d) after selecting memory devices having the selected blocks which are valid, simultaneously programming the selected valid blocks of the selected memory devices; and

(e) checking whether the selected blocks are the last blocks of the respective second storage regions;

(f) designating a next location of each memory device when the selected blocks are not last;

(g) performing the steps (c) through (f) repeatedly until the selected blocks are determined to be the last blocks of the respective second storage regions;

(h) selecting one of the memory devices with at least one invalid block;

(i) programming at least one block of the third storage region of the selected memory device instead of the at least one invalid block thereof;

(j) programming the stored block status information of the selected memory device in the first storage region of the selected memory device;

(k) checking whether the selected device is the last device to be programmed;

(l) selecting a next memory device so long as the selected device is not the last device to be programmed; and

(m) performing the steps (i) through (l) until the selected device is determined to be the last memory device to be programmed.

7. The method according to claim 6, wherein the memory devices share common data and address buses.

8. The method according to claim 6, wherein the method for programming the flash memory devices is performed under the control of a system which comprises a central processing unit, a RAM unit, a ROM unit and an interface unit, wherein the block status information is stored in the RAM unit of the system.