Repair signal generating circuit

• US 6,236,599 B1
• Filed: 07/06/2000
• Issued: 05/22/2001
• Est. Priority Date: 01/25/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Goto, Koji
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US09/610,951
• Time in Patent Office: 320 Days
• Field of Search: 365/194, 365/200, 365/225.7, 365/230.08
• US Class Current: 365/194
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a repair signal generating circuit, a first p-channel transistor has its source connected to a power supply, and a reset signal is input into its gate. An n-channel transistor has its source connected to a terminal of a grounded fuse, its drain connected to the drain of the first p-channel transistor, and the reset signal is input into its gate. A second p-channel transistor has its drain connected to the drains of the first p-channel transistor and the n-channel transistor, and its source connected to the power supply. The on-resistance of the second p-channel transistor is higher than that of the n-channel transistor. An inverter has its input terminal connected to the drains of the first p-channel transistor and the n-channel transistor, and its output terminal, where a repair signal is output, connected to the gate of the second p-channel transistor.

Claims

1. A repair signal generating circuit comprising:

a power supply;

a first p-channel transistor having a source, a gate, and a drain, wherein said source is connected to said power supply, and a reset signal is input into said gate;

a fuse having a grounded first terminal;

an n-channel transistor, having a source, a gate, and a drain, wherein said source is connected to a second terminal of said fuse, the reset signal is input into said gate, and said drain is connected with said drain of said first p-channel transistor;

a second p-channel transistor having a source, a gate, and a drain, wherein said source is connected to said power supply, said drain is connected to said drains of said first p-channel transistor and said n-channel transistor, said second p-channel transistor having an on-resistance higher than that of said n-channel transistor; and

an inverter having an input terminal and an output terminal, wherein said input terminal is connected to said drains of said first p-channel transistor and said n-channel transistor, and said output terminal is connected to said gate of said second p-channel transistor, said inverter outputting a repair signal from said output terminal.

2. The repair signal generating circuit according to claim 1, including a capacitor connected between said power supply and said drains of said first p-channel transistor and said n-channel transistor.

3. The repair signal generating circuit according to claim 1 further comprising a delay circuit for delaying the reset signal representing a reset release, wherein the reset signal representing the reset release is delayed and output to circuits of a semiconductor integrated circuit on which said repair signal generating circuit is mounted.

4. The repair signal generating circuit according to claim 3, wherein said delay circuit comprises a plurality of stages of first flip-flop circuits and the reset signal representing the reset release is delayed and output in synchronization with a system clock supplied to the semiconductor integrated circuit.

5. The repair signal generating circuit according to claim 4 further comprising:

a second flip-flop circuit which latches and outputs the repair signal output by said inverter in response to reset signals output by said plurality of first flip-flop circuits;

a third flip-flop circuit which further delays the reset signals output by said plurality of stages of first flip-flop circuits; and

a reset signal input circuit which produces an AND result of an inversion of the reset signal output by said third flip-flop circuit and the reset signal to be input into said repair signal generating circuit, and outputs the AND result to said gates of said first p-channel transistor and said n-channel transistor.