Power consumption reduction in medical devices employing multiple supple voltages and clock frequency control

• US 6,236,888 B1
• Filed: 03/22/2000
• Issued: 05/22/2001
• Est. Priority Date: 04/29/1998
• Status: Expired due to Term

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Thompson, David L.
• Primary Examiner(s): EVANISKO, GEORGE ROBERT
• Application Number:
  US09/532,623
• Time in Patent Office: 426 Days
• Field of Search: 607/1-5, 607/9, 607/16
• US Class Current: 607/16
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/3605 Implantable neurostimulators for stimulating central or peripheral nerve system
• CPC Class Codes: A61N 1/362 Heart stimulators heart defibrillators A61N1/39
• CPC Class Codes: A61N 1/372 Arrangements in connection with the implantation of stimulators
• CPC Class Codes: A61N 1/378 Electrical supply

Abstract

Power consumption in medical devices is reduced through the operation of circuits at clock speeds of lower levels to adequately complete desired functions during predetermined time periods (e.g., blanking interval, upper rate interval, etc.) just-in-time prior to subsequent required functional processes; by providing supply voltages tailored for various circuits of an integrated circuit; by operating two or more circuits of an integrated circuit at different clock frequencies; by changing the supply voltage level “on the fly” as required by specific circuit timing functions required for various circuitry based on clock frequencies used to control operation of such circuitry; and/or by tailoring back gate bias or adjusting back gate bias “on the fly” for circuits based on the supply voltage level applied to the circuits.

Claims

1. A method for conserving power for a medical device, the method comprising the steps of:

providing one or more circuits operable to perform at least one function during a predetermined time period that extends from the end of a prior time period and the beginning of a subsequent time period, wherein at least one of the circuits is operable for completing the at least one function in a predetermined number of clock cycles;

providing a clock;

operating said clock to generate a clock signal at a minimal clock frequency that provides said predetermined number of clock cycles within said predetermined time period; and

applying said clock signal to the at least one circuit during the predetermined time period to operate the at least one circuit at said clock frequency such that substantially the entire predetermined time period is used to perform the at least one function, wherein the function is completed within the predetermined time period and just prior to the commencement of the subsequent time period.

2. The method of claim 1, wherein the one or more circuits comprise at least a first logic circuit for performing a first function during a first predetermined time period that extends from the end of a prior time period and the beginning of a subsequent time period and a second logic circuit for performing a second function during a second predetermined time period that extends from the end of a prior time period and the beginning of a subsequent time period, and further wherein;

the clock operating step includes the further steps of;

operating said clock to generate a first clock signal at the minimal clock frequency that provides a predetermined number of clock cycles within said first predetermined time period; and

operating said clock to generate a second clock signal at the minimal clock frequency that provides a predetermined number of clock cycles within said second predetermined time period; and

the applying step includes the further steps of;

applying the first clock signal to the first logic circuit to operate the first logic circuit to perform the first function during the predetermined time period at the first clock frequency such that substantially the entire first predetermined time period is used by the first logic circuit to perform the first function; and

applying the second clock signal to the second logic circuit to operate the second logic circuit at the second clock frequency that is different than the first clock frequency such that substantially the entire respective second predetermined time period is used by the second logic circuit to perform the second functions.

3. The method of claim 2, wherein at least one of the first predetermined time period and the second predetermined time period is a time period based on physiological events.

4. The method of claim 2, wherein the at least one of the first and second predetermined time periods are time periods selected from a group of time periods associated with cardiac events including blanking interval, upper rate interval, escape interval, refractory interval, and pulse generator/programmer handshake.

5. The method of claim 1, wherein the one or more circuits comprise a processing device, the processing device operable to perform a plurality of functions, each of the plurality of functions being performed during an associated predetermined time period prior to a subsequent time period in which another of the plurality of functions is performed, each of the plurality of functions requiring a predetermined number of clock cycles of a clock signal, and further wherein the operating step includes:

operating the clock during each associated predetermined time period to generate a clock signal at the minimal clock frequency that provides said predetermined number of clock cycles within said predetermined time period, whereby said processing device is operated at a clock frequency to perform at least one function of the plurality of functions such that substantially the entire associated predetermined time period for the at least one function is used to complete the first function prior to a subsequent time period in which another of the plurality of functions is performed.

6. The method of claim 5, wherein the associated predetermined time period is a time period based on physiological events.

7. The method of claim 6, wherein the associated time period is a time period selected from a group of time periods associated with cardiac events including blanking interval, upper rate interval, escape interval, refractory interval, and pulse generator/programmer handshake.

8. The method of claim 1, wherein the method further includes controlling the level of a supply voltage applied to the at least one circuit as a function of the clock frequency.

9. The device of claim 1, wherein the step of providing one or more circuits further comprises the step of providing circuits of at least one type selected from the group consisting of CMOS circuits, CML circuits, SOS circuits, SOI circuits, BICMOS circuits, PMOS circuits and NMOS circuits.

10. The method of claim 1, wherein the implantable medical device is selected from the group consisting of an implantable stimulator, an implantable nerve stimulator, an implantable pacemaker, an IPG, an implantable cardioverter, an implantable PCD, an implantable defibrillator, an implantable ICD and an implantable drug pump.

11. The method of claim 1 further comprising:

supplying a supply voltage to each one of said circuits, the supply voltage tailored to the plurality of circuits;

changing the supply voltage level on the fly as required by specific circuit timing functions; and

tailoring back gate bias or adjusting back gate bias on the fly for the circuits based on the supply voltage level applied to the circuits.

12. A method of limiting power consumption in a medical device using circuit schemes adapted to the medical device, comprising:

providing a plurality of circuits, each circuit operable to perform a function during a predetermined time period and in a predetermined number of clock cycles, each predetermined time period extending from the end of a prior time period to the beginning of a subsequent time period;

providing a clock;

operating said clock to generate a clock signal at the minimal clock frequency that provides said a predetermined number of clock cycles within said predetermined time period for each circuit;

applying each clock signal to each circuit during each predetermined time period to operate said plurality of circuits at minimal clock speeds;

supplying voltages tailored for the plurality of circuits;

changing the supply voltage level on the fly as required by specific circuit timing functions; and

tailoring back gate bias or adjusting back gate bias on the fly for the circuits based on the supply voltage level applied to the circuits.

13. The method according to claim 12 wherein each clock frequency is selected to provide a minimal number of clock cycles during each predetermined time period to perform the circuit function, whereby substantially the entire predetermined time period is used to perform the circuit function so that the circuit function is completed within the predetermined time period and just prior to the commencement of the subsequent time period.