Method and apparatus for adaptable digital protocol processing

• US 6,237,029 B1
• Filed: 02/26/1996
• Issued: 05/22/2001
• Est. Priority Date: 02/26/1996
• Status: Expired due to Term

• Current Assignee: Argosystems Inc (The Boeing Co.)
• Original Assignee: Argosystems Inc (The Boeing Co.)
• Inventors: Master, Paul L., Hatley, William T., Scheuermann, Walter J. II, Goodman, Margaret J.
• Primary Examiner(s): Maung, Zarni
• Application Number:
  US08/606,714
• Time in Patent Office: 1,912 Days
• Field of Search: 395/200.47, 395/200.49, 395/200.54, 395/200.6, 395/285, 709/217, 709/219, 709/224, 709/230, 710/105
• US Class Current: 709/217
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H04L 2012/5672 Multiplexing, e.g. coding, scrambling
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/24 Negotiation of communication capabilities
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

Processor methods and apparatus for adaptable network processing having speed advantages often associated with hardware implementations of network processing code or logic, as is often achieved using ASICs, for example, but at the same time having reconfigurability advantages often associated with software implementations of this code or logic. Methods and apparatus are described for adaptable hardware devices, such as a field programmable gate array (FPGA) or a circuit using FPGAs, to execute network processing code or logic. Methods and apparatus are described for using a software based device to program adaptable hardware devices to implement desired network processing code or logic.

Claims

1. A network processor comprising:

a computer system;

an adaptable hardware device having an information input wherein the adaptable hardware device provides configurable logic;

an input/output module coupled to the information input of the adaptable hardware device such that the input/output module is adapted to provide to the information input a data stream having a protocol format wherein the adaptable hardware device is adapted to provide the data stream to the configurable logic;

a bus coupling the adaptable hardware device to the computer system wherein the computer system is adapted to communicate with the adaptable hardware device using the bus, wherein the computer system is adapted to configure the configurable logic of the adaptable hardware device into an analysis configuration, wherein the computer system is adapted to use the configurable logic in the analysis configuration to determine the protocol format of the data stream applied to the information input, wherein the computer system is adapted to configure the configurable logic of the adaptable hardware device into a processing configuration associated with the determined protocol format of the data stream and wherein the configurable logic in the processing configuration is adapted to process the data stream having the protocol format.

2. The network processor of claim 1, wherein the computer system is adapted to change the configuration of the configurable logic in real time, and wherein the configurable logic is adapted to be changed in real time between the analysis configuration and the processing configuration.

3. The network processor of claim 1, wherein configurable logic comprises a field programmable gate array.

4. The network processor of claim 3, wherein the field programmable gate array is adapted to be configured by the computer system to provide the analysis configuration and is adapted to be configured by the computer system to provide the processing configuration.

5. The network processor of claim 4, wherein the computer system is adapted to change the configuration of the configurable logic in real time, and wherein the configurable logic is adapted to be changed in real time between the analysis configuration and the processing configuration.

6. The network processor of claim 5, wherein the computer system is adapted to change the configuration of the configurable logic without manual input.

7. The network processor of claim 4, wherein the computer system is adapted to configure the field programmable gate array to provide the analysis configuration by downloading into the field programmable gate array an analysis configuration file and wherein the computer system is adapted to configure the field programmable gate array to provide the processing configuration by downloading into the field programmable gate array a processing configuration file.

8. The network processor of claim 1, wherein the configurable logic comprises a plurality of field programmable gate arrays.

9. The network processor of claim 8, wherein the plurality of field programmable gate arrays are adapted to be configured by the computer system to provide the analysis configuration and are adapted to be configured by the computer system to provide the processing configuration.

10. The network processor of claim 9, wherein the computer system is adapted to change the configuration of the configurable logic in real time, and wherein the configurable logic is adapted to be changed in real time between the analysis configuration and the processing configuration.

11. The network processor of claim 10, wherein the computer system is adapted to change the configuration of the configurable logic without manual input.

12. The network processor of claim 9, wherein the adaptable hardware device further comprises a configurable bus which is adapted to be configured to couple the plurality of field programmable gate arrays to provide the analysis configuration and which is adapted to be configured to couple the plurality of field programmable gate arrays to provide the the processing configuration.

13. The network processor of claim 12, wherein the computer system is adapted to configure the plurality of field programmable gate arrays and the configurable bus to provide the analysis configuration by downloading into each gate array an analysis configuration file and wherein the computer system is adapted to configure the plurality of field programmable gate arrays and the configurable bus to provide the processing configuration by downloading into each field programmable gate array a processing configuration file.

14. The network processor of claim 9, wherein the computer system is adapted to configure the plurality of field programmable gate arrays to provide the analysis configuration by downloading into each gate array an analysis configuration file and wherein the computer system is adapted to configure the plurality of field programmable gate arrays to provide the processing configuration by downloading into each field programmable gate array a processing configuration file.

15. The network processor of claim 1, wherein the computer system is adapted to change the configuration of the configurable logic without manual input.

16. The network processor of claim 1, wherein the computer system is adapted to configure the configurable logic into the analysis configuration by downloading into the configurable logic at least one configuration file associated with the analysis configuration, and wherein the computer system is adapted to configure the configurable logic into the processing configuration by downloading into the adaptable hardware device at least one configuration file associated with the processing configuration.

17. The network processor of claim 1, wherein the processing configuration is adapted to demultiplex the protocol format into a plurality of channels.

18. The network processor of claim 1, wherein

the protocol format comprises a plurality of protocol levels;

the plurality of protocol levels successively increase in level from a lowest level to a highest level;

each protocol level has a protocol format associated with the protocol level;

the computer system is adapted to configure the configurable logic into a plurality of processing configurations wherein the plurality of processing configurations include the processing configuration;

a first of the processing configurations is adapted to process the protocol format of the data stream at the lowest level; and

each of the other processing configurations is adapted to process the protocol format of the data stream at one of the levels above the lowest level.

19. The network processor of claim 18, wherein

the computer system is adapted to use the analysis configuration to determine the protocol format associated with each protocol level;

and

the computer system is adapted to configure the configurable logic into each of the processing configurations in response to the determination of the protocol formats.

20. The network processor of claim 19, wherein the computer system is adapted to change configuration of the configurable logic without manual input.

21. The network processor of claim 18, wherein the protocol format of the lowest level comprises a multiplexing format.

22. The network processor of claim 21, wherein the computer system is adapted to change the configuration of the configurable logic in real time, and wherein the configurable logic is adapted to be changed in real time between the analysis configuration and each of the processing configurations.

23. The network processor of claim 22, wherein the computer system is adapted to change configuration of the configurable logic without manual input.

24. The network processor of claim 18, wherein at least one of the processing configurations is adapted to demultiplex the data stream.

25. The network processor of claim 24, wherein the processing configuration that is adapted to demultiplex the data stream is the processing configuration associated with the lowest level.

26. The network processor of claim 25, wherein the data stream is demultiplexed into a plurality of channels each channel having a protocol format.

27. The network processor of claim 26, wherein the protocol format of at least one of the channels provides the plurality of protocol levels.

28. The network processor of claim 18, wherein the protocol format of the highest level is encapsulated in the protocol format of any levels below the highest level.

29. The network processor of claim 18, wherein at least one of the processing configurations is adapted to deencapsulate a first of the protocol formats from within a second of the protocol formats.

30. The network processor of claim 18, wherein the computer system is adapted to change the configuration of the configurable logic in real time, and wherein the configurable logic is adapted to be changed in real time between the analysis configuration and each of the processing configurations.

31. The network processor of claim 30, wherein the computer system is adapted to change configuration of the configurable logic without manual input.

32. The network processor of claim 18, wherein the computer system is adapted to change the configuration of the configurable logic without manual input.

33. The network processor of claim 1, wherein the protocol format is one of a plurality of possible protocol formats identifiable by the computer system using the analysis configuration.

34. The network processor of claim 1, further comprising a plurality of configuration files that the computer system can use to provide a plurality of configurations of the adaptable hardware device.

35. A network processor comprising:

a computer system;

an adaptable hardware device having an information input wherein the adaptable hardware device provides configurable logic;

an input/output module coupled to the information input of the adaptable hardware device such that the input/output module is adapted to provide to the information input a data stream having one of a first and a second protocol format wherein the adaptable hardware device is adapted to provide to the configurable logic the data stream and wherein the first and second protocol formats are at different protocol levels;

a bus coupling the adaptable hardware device to the computer system wherein the computer system is adapted to communicate with the adaptable hardware device using the bus, wherein the computer system is adapted to determine the protocol format of the data stream, wherein the computer system is adapted to configure the configurable logic into a first processing configuration when the data stream has the first protocol format and wherein the computer system is adapted to configure the configurable logic into a second processing configuration when the data stream has the second protocol format, wherein the configurable logic in the first processing configuration is adapted to process the data stream having the first protocol format and wherein the configurable logic in the second processing configuration is adapted to process the data stream having the second protocol format.

36. A network processor comprising:

a computer system;

an adaptable hardware device having an information input wherein the adaptable hardware device provides configurable logic;

an input/output module coupled to the information input of the adaptable hardware device such that the input/output module is adapted to provide to the information input a data stream having a protocol format wherein the adaptable hardware device can be configured to provide the data stream to the configurable logic;

a bus coupling the adaptable hardware device to the computer system wherein the computer system is adapted to communicate with the adaptable hardware device using the bus, wherein the computer system is adapted to determine the protocol format of the data stream without manual input that identifies the protocol format of the data stream, wherein the computer system is adapted to configure the configurable logic into a processing configuration and wherein the configurable logic in the processing configuration is adapted to process the data stream having the protocol format;

a plurality of configuration files that the computer system can use to provide a plurality of hardware configurations of the adaptable hardware device.