Supporting multiple outstanding requests to multiple targets in a pipelined memory system

• US 6,237,066 B1
• Filed: 03/22/1999
• Issued: 05/22/2001
• Est. Priority Date: 03/22/1999
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Pan, Bi-Yu, Tremblay, Marc
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/273,850
• Time in Patent Office: 792 Days
• Field of Search: 711/117, 711/118, 711/131, 711/149, 711/156, 711/168, 710/39, 710/52, 712/9
• US Class Current: 711/149
• CPC Class Codes: G06F 9/3824 Operand accessing

Abstract

One embodiment of the present invention provides an apparatus that supports multiple outstanding load and/or store requests from an execution engine to multiple sources of data in a computer system. This apparatus includes a load store unit coupled to the execution engine, a first data source and a second data source. This load store unit includes a load address buffer, which contains addresses for multiple outstanding load requests. The load store unit also includes a controller that coordinates data flow between the load address buffer, a register file, the first data source and the second data source so that multiple load requests can simultaneously be outstanding for both the first data source and the second data source. These load requests return in-order for each of the multiple sources of data in the computer system, except for load requests directed to a data cache which can return out-of-order. Load requests may return out-of-order with respect to load requests from other data sources. According to one aspect of the present invention, the load store unit additionally includes a store address buffer, that contains addresses for multiple outstanding store requests, and a store data buffer that contains data for the multiple outstanding store requests. The controller is further configured to coordinate data flow between the first data source, the second data source, the store address buffer and the store data buffer, so that multiple store requests can simultaneously be outstanding for both the first data source and the second data source.

Claims

1. An apparatus that supports multiple outstanding load requests from an execution engine to multiple sources of data in a computer system including a data cache, the apparatus comprising:

a load store unit coupled to the execution engine, a first data source and a second data source, wherein the first data source is the data cache;

a first data port within the load store unit coupled to the first data source;

a second data port within the load store unit coupled to the second data source, so that the load store unit can simultaneously send load requests to the first data source and the second data source;

a load address buffer within the load store unit, that contains addresses for multiple outstanding load requests;

a register file for storing data received by the load store unit during a load request; and

a controller that is configured to coordinate data flow between the load address buffer, the register file, the first data source and the second data source, so that multiple load requests can simultaneously be outstanding for both the first data source and the second data source.

2. The apparatus of claim 1, further comprising:

a store address buffer, that contains addresses for multiple outstanding store requests;

a store data buffer that contains data for the multiple outstanding store requests; and

wherein the controller is configured to coordinate data flow between the first data source, the second data source, the store address buffer and the store data buffer, so that multiple store requests can simultaneously be outstanding for both the first data source and the second data source.

3. The apparatus of claim 1, wherein the load store unit is additionally coupled to a third data source through a third data port so that the load store unit can send multiple load requests to the first data source, the second data source, and the third data source simultaneously, and wherein the controller is configured to coordinate data flow so that multiple load requests can simultaneously be outstanding for the first data source, the second data source and the third data source.

4. The apparatus of claim 1, wherein the load store unit is coupled to the data cache through a first communication pathway, and is coupled to the second data source through a second communication pathway that is separate from the first communication pathway.

5. The apparatus of claim 1, wherein the controller is configured so that load requests return in-order for each of the multiple sources of data in the computer system, except for load requests directed to a data cache which can return out-of-order.

6. The apparatus of claim 5, wherein the controller is configured so that load requests can return out-of-order with respect to load requests from other data sources.

7. The apparatus of claim 1, wherein the controller is configured so that multiple load requests can be sent to different data sources in the same clock cycle.

8. The apparatus of claim 1, wherein the controller includes a separate state machine for each entry in the load address buffer.

9. The apparatus of claim 1, wherein the second data source includes an interface to a computer system bus.

10. The apparatus of claim 1, wherein the second data source includes a random access semiconductor memory.

11. The apparatus of claim 1, wherein the second data source includes a secondary storage device.

12. The apparatus of claim 1, wherein the second data source includes one of a computer graphics accelerator, a processor and a bridge chip.

13. The apparatus of claim 1, wherein each entry in the load address buffer is associated with status information indicating a target for the load request, wherein the target may include one of the first data source and the second data source.

14. The apparatus of claim 1, wherein each entry in the load address buffer is associated with status information indicating whether data received during an associated load request is cacheable.

15. The apparatus of claim 1, wherein each entry in the load address buffer is associated with status information indicating a state of an associated load request.

16. The apparatus of claim 1, wherein each entry in the load address buffer is associated with status information indicating a destination register of an associated load request.

17. The apparatus of claim 1, further comprising alignment circuitry for aligning data received during the load request before it is stored in the register file.

18. An apparatus that supports multiple outstanding load and store requests from an execution engine to multiple sources of data in a computer system including a data cache, the apparatus comprising:

a load store unit coupled to the execution engine, a first data source and a second data source, wherein the first data source is the data cache;

a first data port within the load store unit coupled to the first data source;

a second data port within the load store unit coupled to the second data source, so that the load store unit can simultaneously send load requests to the first data source and the second data source;

a load address buffer within the load store unit, that contains addresses for multiple outstanding load requests;

a register file for storing data received by the load store unit during a load request;

a store address buffer, that contains addresses for multiple outstanding store requests;

a store data buffer, that contains data for the multiple outstanding store requests; and

a controller that is configured to coordinate data flow between the load address buffer, the register file, the first data source and the second data source, so that multiple load requests can simultaneously be outstanding for both the first data source and the second data source;

wherein the controller is additionally configured to coordinate data flow between the first data source, the second data source, the store address buffer and the store data buffer, so that multiple store requests can simultaneously be outstanding for both the first data source and the second data source.

19. The apparatus of claim 18, wherein the load store unit is additionally coupled to a third data source through a third data port so that the load store unit can send multiple load requests to the first data source, the second data source, and the third data source simultaneously, and wherein the controller is configured to coordinate data flow so that multiple load requests can simultaneously be outstanding for the first data source, the second data source and the third data source.

20. The apparatus of claim 18, wherein the load store unit is coupled to the data cache through a first communication pathway, and is coupled to the second data source through a second communication pathway that is separate from the first communication pathway.

21. The apparatus of claim 18, wherein the controller is configured so that load requests return in-order for each of the multiple sources of data in the computer system, except for load requests directed to a data cache which can return out-of-order.

22. The apparatus of claim 18, wherein the controller is configured so that load requests can return out-of-order with respect to load requests from other data sources.

23. A method for supporting multiple outstanding load requests from an execution engine to multiple sources of data in a computer system including a data cache, the method comprising:

receiving a load request from the execution engine, the load request specifying one of a first data source and a second data source, wherein the first data source is coupled to a first data port within the load store unit and the second data source is coupled to a second data port within the load store unit so that the load store unit can simultaneously send load requests to the first data source and the second data source;

storing an address from the load request in a load address buffer, the load address buffer containing addresses for multiple outstanding load requests so that multiple load requests can simultaneously be outstanding for both the first data source and the second data source;

sending the load request to one of the first data source and the second data source, wherein the first data source is the data cache; and

in response to the load request, receiving data from one of the first data source and the second data source in a register file.

24. The method of claim 23, further comprising:

receiving a store request from the execution engine;

storing an address from the store request in a store address buffer, the store address buffer containing addresses for multiple outstanding store requests so that multiple store requests can simultaneously be outstanding for both the first data source and the second data source; and

storing data from the store request in a store data buffer, the store data buffer containing data from the multiple outstanding store requests.

25. The method of claim 23, wherein the load request may additionally be directed to a third data source through a third data port so that the load store unit can send multiple load requests to the first data source, the second data source, and the third data source simultaneously, and wherein multiple load requests can simultaneously be outstanding for the first data source, the second data source and the third data source.

26. The method of claim 23, wherein sending the load request to one of the first data source and the second data source involves sending the load request through a first communication pathway to the first data source, and through a second communication pathway to the second data source, wherein the second communication pathway is separate from the first communication pathway.

27. The method of claim 23, wherein the act of receiving the data from one of the first data source and the second data source, involves receiving the data in order from the second data source, and receiving data out-of-order from the first data source.

28. The method of claim 27, wherein the act of receiving the data from one of the first data source and the second data source, includes receiving the data from a third data source, wherein the data may be received out-of-order as between the second data source and a third data source.