Coprocessor interface having pending instructions queue and clean-up queue and dynamically allocating memory

• US 6,237,079 B1
• Filed: 02/18/1998
• Issued: 05/22/2001
• Est. Priority Date: 04/30/1997
• Status: Expired due to Term

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Stoney, Graham
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US09/025,758
• Time in Patent Office: 1,189 Days
• Field of Search: 711/147, 711/148, 711/153, 712/34, 712/35
• US Class Current: 712/34
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering

Abstract

The present invention discloses a method of controlling the interaction of a host CPU (202) and at least one co-processor (224) in a computer system (201) to permit substantially simultaneous decoupled execution of CPU instructions and co-processor instructions. The co-processor instructions to be executed, and those which have been executed are allocated to respective queues (1040, 1041). From time to time the latter queue (1041) is cleaned up under control of the CPU (202) to release memory resources previously allocated to the co-processor by the CPU. This dynamic memory management arrangement preferably includes an instruction generator (1030), a memory manager (1031) and a queue manager (1032).

Claims

1. A method of controlling the interaction between a host CPU and at least one co-processor in a computer system to permit substantially simultaneous decoupled execution of CPU instructions and co-processor instructions, and dynamic allocation of commonly used memory space during the course of the execution of said instructions, said method comprising the steps of:

(a) said host CPU allocating memory resources to be utilized by a set of instructions to be co-processor executed;

(b) generating a queue of pending co-processor instructions to be executed and a clean up queue of co-processor instructions for which execution has been completed;

(c) from time to time, under control of said host CPU, releasing for reallocation memory resources previously utilized by the instructions contained in said clean up queue of executed instructions.

2. A method as claimed in claim 1 wherein step (c) is carried out following execution by the co-processor of a predetermined instruction.

3. A method as claimed in claim 2 wherein said predetermined instruction is one which utilizes very substantial memory resources.

4. A method as claimed in claim 2 wherein said predetermined instruction is the last instruction in said pending instruction queue.

5. A method as claimed in claim 1 wherein step (c) is carried out when said host CPU detects that currently free memory resources are running low or are exhausted.

6. A method as claimed in claim 5 wherein further processing by said host CPU is interrupted and step (c) is carried out after a predetermined fraction of said queue of pending co-processor instructions have been executed.

7. A method as claimed in claim 6 wherein said predetermined fraction is selected from the group consisting of one third, one half and two thirds.

8. A method as claimed in claim 6 wherein step (c) is carried out after a predetermined number of the pending instructions in said queue of co-processor instructions have been executed.

9. A method as claimed in claim 1 wherein step (a) allocates instructions for a single co-processor.

10. Dynamic memory management means in a computer system having a memory of predetermined size, a host CPU and at least one co-processor, said memory management means comprising:

(a) an instruction generator means connected with said host CPU and generating a sequence of instructions intended for co-processor execution,

(b) a memory manager means connected to said memory and said instruction generator means to dynamically allocate space in said memory for co-processor use in executing said sequence of co-processor instructions,

(c) a queue manager means connected to said instruction generator means, said memory manager means and said co-processor, said queue manager means being arranged to store said sequence of instructions in a queue of pending instructions to be co-processor executed and a clean up queue of instructions which have been co-processor executed,

wherein from time to time said queue manager means removes executed instructions from said clean up queue to thereby release for reallocation memory space previously allocated to said removed executed instructions.

11. The dynamic memory management means as claimed in claim 10 wherein if said memory manager means is unable to satisfy a request for memory space, said queue manager means is triggered to remove said executed instructions from said clean up queue.

12. The dynamic memory management means as claimed in claim 11 wherein if after removal of said executed instructions from said clean up queue said memory manager means is still unable to satisfy a request for memory space, further processing by said CPU is interrupted until a predetermined fraction of said queue of pending co-processor instructions has been co-processor executed.

13. The dynamic memory management means as claimed in claim 12 wherein said pre-determined fraction is selected from the group consisting of one third, one half, and two thirds.

14. The dynamic memory management means as claimed in claim 12 wherein further processing by said CPU is interrupted until a predetermined number of said instructions in said queue of pending co-processor instructions have been co-processor executed.

15. The dynamic memory management means as claimed in claim 14 wherein said predetermined number corresponds to the entire length of said queue of pending co-processor instructions.