Signal processor with intelligent feedback to ensure functionality of microprocessor and state machine based programmable pulse generators in the presence of clock and power supply disturbances

• US 6,237,105 B1
• Filed: 04/26/1993
• Issued: 05/22/2001
• Est. Priority Date: 04/26/1993
• Status: Expired due to Term

• Current Assignee: Dwight N. Holmbo
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Walsh, Kevin K., Korsunsky, Roman, Reinke, James D.
• Primary Examiner(s): Banankhah, Majid A.
• Application Number:
  US08/054,496
• Time in Patent Office: 2,948 Days
• Field of Search: 395/550, 395/307, 395/269, 307/265, 307/267, 370/58, 235/153.AC, 713/400, 713/401, 713/500, 713/600
• US Class Current: 713/500
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom

Abstract

A signal processor operates on a microprocessor or state machine based system to ensure that the central processing unit (CPU) and pulse generator (PG) have finished their instructions before allowing a new transition on the system master clock. The CPU and PG contain circuitry which allows them to indicate when they are busy. These signals are fed to the signal processor to indicate when the CPU and PG are ready to start another instruction. The signal processor functions to prevent a noise glitch on the system clock from causing another operation to start before the one in process has finished. The output of the signal processor becomes the master clock signal used by the system.

Claims

1. A clock circuit for providing a main clock signal having periodic logic state transitions to an associated circuit which performs actions in response to said logic state transitions of said main clock signal and provides completion signals indicating completion of said actions performed in response to a preceding logic state transition of said main clock signal, wherein said clock circuit comprises:

a main clock output means for providing said main clock signal to said associated circuit;

a clock signal input means for receiving an input clock signal having periodic logic state transitions;

completion signal input means for receiving said completion signals from said associated circuit;

means responsive to occurrence of a logic state transition of said input clock signal for causing a logic state transition of said main clock signal, said responsive means further comprising logic means responsive to receipt of a said completion signal indicating completion of actions performed in response to a preceding logic state transition of said main clock signal, for delaying said transition of said logic state of said main clock signal until receipt of said completion signal.

2. A clock circuit as in claim 1, wherein said logic means further comprises first delay means for providing a delayed completion signal a first delay interval after receipt of a said completion signal and wherein said logic means comprises means for delaying a transition of said logic state of said main clock signal until occurrence of said delayed completion signal.

3. A clock circuit as in claim 1, wherein said completion signal input means comprises means for preventing receipt of a said completion signal until expiration of a second delay interval following an immediately preceding logic state transition of said main clock signal.

4. A clock circuit for providing a main clock signal having periodic logic state transitions to an associated circuit which performs actions in response to said logic state transitions of said main clock signal and provides a plurality of completion signals each indicating completion of actions performed in response to a preceding logic state transition of said main clock signal, said clock circuit comprising:

a main clock output means for providing said main clock signal to said associated circuit;

a clock signal input means for receiving an input clock signal having periodic logic state transitions;

completion signal input means for receiving said plurality of completion signals from said associated circuit;

means responsive to occurrence of a logic state transition of said input clock signal for causing a logic state transition of said main clock signal said responsive mans further comprising logic means responsive to receipt of a said completion signal indicating completion of actions performed in response to a preceding logic state transition of said main clock signal for delaying said transition of said logic state of said main clock signal until receipt of said plurality of completion signals.

5. A system comprising a clock circuit for providing a main clock signal having periodic logic state transitions and an associated circuit which performs actions in response to said logic state transitions of said main clock signal wherein said associated circuit comprises means for providing completion signals indicating completion of said actions performed in response to a preceding logic state transition of said main clock signal, and wherein said clock circuit comprises a main clock output means for providing said main clock signal to said associated circuit, a clock signal input means for receiving an input clock signal having periodic logic state transitions completion signal input means for receiving said completion signals from said associated circuit and means responsive to occurrence of a logic state transition of said input clock signal for causing a logic state transition of said main clock signal, said responsive means further comprising logic means responsive to receipt of a said completion signal indicating completion of actions performed in response to a preceding logic state transition of said main clock signal for delaying a said transition of said logic state of said main clock signal until receipt of a said completion signal.

6. A system as in claim 5, wherein said logic means further comprises first delay means for providing a delayed completion signal a first delay interval after receipt of a said completion signal and wherein said logic means comprises means for delaying said transition of said logic state of said main clock signal until occurrence of said delayed completion signal.

7. A system circuit as in claim 5, wherein said completion signal input means comprises means for preventing receipt of a said completion signal until expiration of a second delay interval following an immediately preceding logic state transition of said main clock signal.

8. A system comprising a clock circuit for providing a main clock signal having periodic logic state transitions and an associated circuit which performs actions in response to said logic state transitions of said main clock signal, wherein said associated circuit comprises means for providing a plurality of completion signals each indicating completion of actions performed in response to a preceding logic state transition of said main clock signal, and wherein said clock circuit comprises a main clock output means for providing said main clock signal to said associated circuit, a clock signal input means for receiving an input clock signal having periodic logic state transitions, completion signal input means for receiving said plurality of completion signals from said associated circuit and means responsive to occurrence of a logic state transition of said input clock signal for causing a logic state transition of said main clock signal, said responsive means further comprising logic means responsive to receipt of a said completion signal indicating completion of actions performed in response to a preceding logic state transition of said main clock signal for delaying a said transition of said logic state of said main clock signal until receipt of said plurality of completion signals.