Dual barrier and conductor deposition in a dual damascene process for semiconductors

• US 6,239,021 B1
• Filed: 09/05/2000
• Issued: 05/29/2001
• Est. Priority Date: 05/24/1999
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pramanick, Shekhar, Brown, Dirk, Iacoponi, John A.
• Primary Examiner(s): Lee, Eddie C.
• Assistant Examiner(s): Brock, II, Paul E
• Application Number:
  US09/655,110
• Time in Patent Office: 266 Days
• Field of Search: 438/622, 438/624, 438/625, 438/627, 438/628, 438/629, 438/631, 438/634, 438/637, 438/641, 438/642, 438/643, 438/644, 438/645, 438/648, 438/650, 438/653, 438/656, 438/687
• US Class Current: 438/627
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53242 the principal metal being a noble metal, e.g. gold
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/915 with titanium nitride portion or region

Abstract

An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.

Claims

1. A method of manufacturing an integrated circuit, comprising the steps of:

providing a semiconductor device with a first dielectric layer formed thereon;

forming an opening in said first dielectric layer in contact with said semiconductor device;

filling said opening with a conductive material;

forming a second dielectric layer on said first dielectric layer;

forming a via opening and a second opening in said second dielectric layer, said via opening connected to said conductive material, said second opening connected to said via opening;

forming a barrier layer to line said via opening, said barrier layer formed in contact with said conductive material;

forming a seed layer to line said barrier layer;

filling said via opening with a second conductive material over said seed layer;

forming a second barrier layer over said second conductive material and lining said second opening;

forming a second seed layer to line said second barrier layer;

filling said second opening with a third conductive material over said second seed layer; and

removing said conductive materials and said layers outside said second opening to expose said second dielectric layer.

2. The method as claimed in claim 1 including the steps of:

forming a barrier layer in said opening in said first dielectric layer; and

forming a seed layer to line said barrier layer in said opening in said first dielectric layer.

3. The method as claimed in claim 1 wherein one of the steps of forming said barrier layer uses a material selected from a group consisting of tantalum, titanium, tungsten, alloys thereof, compounds thereof, and combinations thereof.

4. The method as claimed in claim 1 wherein one of the steps of forming said seed layer uses a material selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.

5. The method as claimed in claim 1 wherein one of the steps of filling said opening with a conductive material uses a material selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.

6. A method of manufacturing an integrated circuit, comprising the steps of:

providing a semiconductor device with a first dielectric layer formed thereon;

forming an opening in said first dielectric layer in contact with said semiconductor device;

filling said opening with a conductive material;

forming a via dielectric layer on said first dielectric layer;

forming a second dielectric layer on said via dielectric layer;

forming a via opening in said via dielectric layer and a second opening in said second dielectric layer, said via opening defined by walls of said via dielectric layer and connected to said conductive material, said second opening defined by walls of said second dielectric layer and connected to said via opening;

forming a barrier layer to line said via opening and said second opening, said barrier layer formed in contact with said conductive material;

forming a seed layer to line said barrier layer;

filling said via opening with a second conductive material over said seed layer;

forming a second barrier layer over said second conductive material and lining said second opening;

forming a second seed layer to line said second barrier layer;

filling said second opening with a third conductive material over said second seed layer; and

removing said third conductive material, said second seed layer, said second barrier layer, said second conductive material, said seed layer, and said barrier layer outside said second opening to expose said second dielectric layer.

7. The method as claimed in claim 6 including the steps of:

forming a barrier layer in said opening in said first dielectric layer; and

forming a seed layer to line said barrier layer in said opening in said first dielectric layer.

8. The method as claimed in claim 6 wherein the steps of forming said barrier layers use materials selected from a group consisting of tantalum, titanium, tungsten, alloys thereof, compounds thereof, and combinations thereof.

9. The method as claimed in claim 6 wherein the steps of forming said seed layers use materials selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.

10. The method as claimed in claim 6 wherein the steps of filling said opening with conductive materials use materials selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.