Semiconductor gate trench with covered open ends
First Claim
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1. A semiconductor device, comprising:
- a semiconductor substrate;
a diffusion layer containing a high concentration of impurity formed on a surface of the semiconductor substrate;
an insulation film formed on the diffusion layer;
a layer which is formed on the insulation film and has an oxidation rate faster than the semiconductor substrate and the diffusion layer;
trenches formed to pierce the diffusion layer, the insulation film and the layer having a fast oxidation rate; and
an oxidation film formed to cover a sidewall of the trenches;
wherein at least an upper end corner portion of the sidewall of each of the trenches is covered with an oxidation film which is formed by oxidizing the layer having the fast oxidation rate.
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Abstract
A semiconductor device, which can have a uniform film on open ends of trenches by using materials having a different oxidation rate, and a fabrication method thereof are provided. The semiconductor device having trenches configured to have open ends covered with an oxidation film made of a material having an oxidation rate faster than that of a semiconductor substrate and a fabrication method thereof are provided.
93 Citations
3 Claims
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1. A semiconductor device, comprising:
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a semiconductor substrate;
a diffusion layer containing a high concentration of impurity formed on a surface of the semiconductor substrate;
an insulation film formed on the diffusion layer;
a layer which is formed on the insulation film and has an oxidation rate faster than the semiconductor substrate and the diffusion layer;
trenches formed to pierce the diffusion layer, the insulation film and the layer having a fast oxidation rate; and
an oxidation film formed to cover a sidewall of the trenches;
wherein at least an upper end corner portion of the sidewall of each of the trenches is covered with an oxidation film which is formed by oxidizing the layer having the fast oxidation rate. - View Dependent Claims (2, 3)
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsSuzuki, Keita, Tsuchitani, Masanobu, Baba, Yoshiro, Osawa, Akihiko
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Primary Examiner(s)Lee, Eddie C.
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Assistant Examiner(s)Fenty, Jesse A
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Application NumberUS09/226,720Time in Patent Office873 DaysField of Search257/329, 257/330, 257/333, 257/334, 257/332US Class Current257/330CPC Class CodesH01L 29/42368 the thickness being non-uni...H01L 29/4238 characterised by the surfac...H01L 29/66666 Vertical transistors H01L29...
