MIS transistor and manufacturing method thereof

• US 6,239,471 B1
• Filed: 06/04/1997
• Issued: 05/29/2001
• Est. Priority Date: 12/10/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Shimizu, Satoshi, Oda, Hidekazu
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nguyen, Cuong Quang
• Application Number:
  US08/869,172
• Time in Patent Office: 1,455 Days
• Field of Search: 257/900, 257/382-384, 257/392, 257/408-414, 348/300-305
• US Class Current: 257/408
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

This invention provides a MIS transistor with less electrical short between a gate and source/drain electrodes. A sidewall spacer 15 has a two-layer structure including a buffer layer 13 which consists of nitrided oxide silicon and a silicon nitrided layer 14 formed on the buffer layer 13. The sidewall spacer 15 serves as a mask to form a silicide film 10.

Claims

1. A MIS transistor comprising:

a silicon substrate;

a gate insulation film formed on said silicon substrate;

a gate electrode formed on said gate insulation film;

source and drain regions formed in said silicon substrate;

a sidewall spacer formed on sides of said gate electrode on said silicon substrate, said sidewall spacer including a buffer nitrided oxide silicon layer in contact with said silicon substrate adjacent said source and drain regions, and a silicon nitride layer; and

a silicide film outside of said sidewall spacer in said silicon substrate, said silicide film including a metal to be a diffusion species for silicon in silicide reaction wherein said buffer nitrided oxide silicon layer has its peak of nitrogen concentration on an interface with said silicon substrate; and

the nitrogen concentration in said buffer nitrided oxide silicon layer declines with distance from said silicon substrate.

2. The MIS transistor of claim 1, wherein said metal to be diffusion species for silicon consists of cobalt.

3. The MIS transistor of claim 1, wherein said metal to be diffusion species for silicon consists of nickel.

4. The MIS transistor of claim 1, wherein said metal to be diffusion species for silicon consists of alloy including cobalt.

5. The MIS transistor of claim 1, wherein said metal to be diffusion species for silicon consists of alloy including nickel.

6. The MIS transistor of claim 1, wherein said silicon nitride layer is formed only on the sides of said gate electrode.

7. The MIS transistor of claim 1, wherein said buffer nitrided oxide silicon layer is formed only in a portion which is in contact with said silicon substrate adjacent said source and drain regions.