Reduced cross-talk noise high density signal interposer with power and ground wrap

• US 6,239,485 B1
• Filed: 05/20/1999
• Issued: 05/29/2001
• Est. Priority Date: 11/13/1998
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Takahashi, Yasuhito, Lee, Michael G., Wang, Wen-chou Vincent, Chou, William, Peters, Michael G., Beilin, Solomon
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/315,785
• Time in Patent Office: 740 Days
• Field of Search: 257/700, 257/691, 257/781, 257/698, 257/738, 257/778, 257/780, 257/774, 257/777, 257/734, 257/735, 257/736, 257/779, 361/794, 361/795
• US Class Current: 257/700
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0219 : Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/144 : Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/049 : PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/055 : Folded back on itself
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: H05K 3/20 : by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence

Abstract

An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a “U” shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core'"'"'s intermediary power/ground plane.

Claims

1. An interposer for connecting an integrated circuit chip to a mounting substrate, comprising:

a power and ground connection routing structure having a first substrate to which the integrated circuit chip may be interconnected and a second substrate to which the mounting substrate may be interconnected, the first and second substrates including a plurality of conductive vias formed therein for power and ground connection paths between the mounting substrate and a mounted integrated circuit chip; and

a signal line routing structure disposed between the first and second substrates of the power and ground connection routing structure, the signal line routing structure including a conductive substrate on a first and second sides of which is disposed a dielectric layer, with a patterned metal layer disposed on each dielectric layer, and including a plurality of conductive vias formed between the patterned metal layers for signal paths between the first and second substrates of the power and ground connection routing structure,

wherein the power and ground connection paths are substantially isolated from the signal paths so that power is routed through the power and ground connection routing structure without passing through the signal line routing structure.

2. The interposer of claim 1, wherein the power and ground connection routing structure further comprises:

a patterned conductive layer arranged on a first and a second coplanar face of the first substrate, the conductive vias providing electrical connections between the conductive layers on the first and second faces of the first substrate; and

a patterned conductive layer arranged on a first and a second coplanar face of the second substrate, the conductive vias providing electrical connections between the conductive layers on the first and second faces of the second substrate.

3. The interposer of claim 1, further comprising:

a support member to maintain the first and second substrates of the power and ground connection routing structure at a desired separation.

4. The interposer of claim 3, wherein the support member electrically connects the conductive substrate of the signal line routing structure to the power connection paths of the power and ground connection structure.

5. The interposer of claim 2, wherein the power and ground connection routing structure further comprises:

a ground connection path between the first coplanar face of the first substrate and the second coplanar face of the second substrate.

6. The interposer of claim 2, wherein the power and ground connection routing structure further comprises:

a power connection path between the second coplanar face of the first substrate and the first coplanar face of the second substrate.