Method and apparatus for monitoring SOI hysterises effects

• US 6,239,591 B1
• Filed: 04/29/1999
• Issued: 05/29/2001
• Est. Priority Date: 04/29/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Bryant, Andres, Tong, Minh Ho
• Primary Examiner(s): Metjahic, Safet
• Assistant Examiner(s): Nguyen, Jimmy
• Application Number:
  US09/303,358
• Time in Patent Office: 761 Days
• Field of Search: 331/111, 331/57, 340/663, 324/158.1, 324/765, 368/113, 368/118, 439/16-18
• US Class Current: 324/762.05
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A system and method for measuring hysteresis effects of a wafer process. The method comprises steps of generating a pulse having a pulse width equal to the delay of a transition through a delay chain wherein the delay chain has been in a static condition for a substantial length of time; counting a number of oscillations from a ring oscillator generated during the pulse width wherein the ring oscillator has been operating in a steady state condition; comparing the number of oscillations with an expected value; and correlating a difference resulting from the comparing step with a level of hysteresis effected by the wafer process.

Claims

1. Method for measuring SOI floating-body time-delay hysteresis effects of a wafer process, the method comprising:

generating a pulse having a pulse width equal to the delay of a transition through a multi-stage delay chain formed in said wafer, wherein the delay chain has been in a static condition for a substantial length of time, said pulse width representing a delay time corresponding to a first switch delay;

for a time duration equal to said pulse width, counting a number of oscillations from a ring oscillator constructed of the same individual stages that are used in said multi-stage delay chain and operating in steady-state condition, said oscillations of said ring oscillator comprising pulses with each pulse representing an average steady state stage delay time for said ring oscillator, said number of oscillations being proportional to a ratio of said first switch time-delay to said average ring oscillator steady state time-delay; and

comparing the number of oscillations with an expected value, wherein a difference between a measured number of oscillations and said expected value represents deviations in said time-delay hysteresis, said deviations in said time-delay hysteresis correlating to variations in said wafer process.

2. Method for measuring SOI floating-body time-delay hysteresis effects of a wafer process, the method comprising:

generating a first pulse having a first pulse width equal to the delay of a transition through a first delay chain formed in said wafer, said first pulse width representing a delay time corresponding to a first switch delay/stage;

propagating said first pulse through a second delay chain constructed of the same individual stages that are used in said first delay chain, wherein the second delay chain has been in a static condition for a substantial length of time, and obtaining a second pulse at an output of said second delay chain, said second pulse having a second pulse width representing a difference between said first switch/delay per stage and a second switch/delay per stage, said second switch delay being greater than said first switch delay;

for a time duration equal to said second pulse width, counting a number of oscillations from a ring oscillator constructed of the same individual stages that are used in said second and first delay chains and operating in steady-state condition, said oscillations of said ring oscillator comprising pulses with each pulse representing an average steady state stage delay time for said ring oscillator, said number of oscillations being proportional to a ratio between said difference between a first switch/delay per stage and a second switch/delay per stage, and to said ring oscillator average steady state delay;

comparing the number of oscillations with an expected value, wherein a difference between a measured number of oscillations and said expected value represents deviations in said time-delay hysteresis, said deviations in said time-delay hysteresis correlating to variations in said wafer process.

3. Apparatus for measuring SOI floating-body time-delay hysteresis effects of a wafer process comprising:

pulse generator means for generating a pulse having a pulse width equal to a delay of a transition through a multi-stage delay chain formed in said wafer, wherein the delay chain has been in a static condition for a substantial length of time, said pulse width representing a delay time corresponding to a first switch delay;

oscillator means constructed of the same individual stages that are used in said multi-stage delay chain and operating in steady state for generating an oscillation stream of pulses, each pulse representing an oscillator average steady state stage delay time for said ring oscillator;

counter means for counting a number of oscillations from said oscillator means generated during said pulse width, said number of oscillations from said oscillator means being proportional to a ratio of said first switch time-delay to said average steady state time-delay, wherein a difference between a measured number of oscillations and said expected value represents deviations in said time-delay hysteresis, said deviations in said time-delay hysteresis correlating to variations in said wafer process.

4. The apparatus as claimed in claim 3, wherein said multi stage delay chain comprises a serial connection of inserter devices having a first number of stages, said oscillator means comprising a ring oscillator including a serial connection of inverter devices having a second number of stages, wherein said second number of stages is smaller than said first number of stages.

5. The apparatus as claimed in claim 4, wherein said second number of stages comprises about 10% of said first number of stages of said multi stage delay chain.

6. The apparatus as claimed in claim 4, wherein inverter stages of said ring oscillator are of identical physical design as inverter stages of said multi stage delay chain.

7. Apparatus for measuring SOI floating-body time-delay hysteresis effects of a wafer process comprising:

pulse generator means for generating a first pulse having a first narrow pulse width;

multi-stage delay chain for receiving said first pulse and generating a second pulse signal of second pulse width representing wafer hysteresis effects, said multi-stage delay chain having been in a static condition for a substantial length of time, said second pulse width representing a difference between a first switch delay corresponding to a delay caused by propagating a rising edge of said first narrow pulse through said multi-stage delay chain and a second switch delay corresponding to a delay caused by propagating a falling edge of said first narrow pulse through said delay chain;

oscillator means constructed of the same individual stages that are used in said multi-stage delay chain and operating in steady state for generating an oscillation stream of pulses, each pulse representing an oscillator average steady state stage delay time for said ring oscillator;

counter means for counting a number of oscillations from said oscillator means generated during said second pulse width, said number of oscillations from said oscillator means being proportional to a ratio between said difference between a first switch/delay per stage and a second switch/delay per stage of said first pulse through said multi-stage delay chain, and to said ring oscillator average steady state delay, whereby said number of oscillations is compared with a value expected for said wafer process to determine deviations in said time-delay hysteresis correlating to variations in said wafer process.

8. The apparatus as claimed in claim 7, wherein said second switch delay through said multi-stage delay chain is longer than said first switch delay through said multi-stage delay chain.