Monitor TEG test circuit
First Claim
1. A test circuit for a plurality of monitor test element groups (TEGs), which are formed on a semiconductor chip together with a semiconductor device and placed in selected positions scattered in the chip, wherein the test circuit selectively tests the monitor TEGs to thereby monitor variations in process parameters within the chip, the test circuit comprising:
- a TEG control circuit responsive to externally applied test signals T0 and T1 to Tn for outputting control signals G1 to Gn to control the monitor TEGs, respectively; and
at least one data output terminal of the semiconductor device which is diverted by an enable signal to an input terminal for one of the test signals T0 to Tn, wherein the at least one data output terminal of the semiconductor device is connected to an input of the TEG control circuit.
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Accused Products
Abstract
Monitor TEGs (Test Element Groups) for extracting the effects of process variations within a semiconductor chip and a test circuit therefor are provided to allow the monitor TEGs to be tested after package sealing. A plurality of monitor TEGs and a control circuit for selectively enabling the monitor TEGs are formed on the same chip as a semiconductor device is formed. The monitor TEGs are placed in selected positions in the chip and selectively monitored via test signals, thereby implementing process parameter monitoring by means of the device parameter variations within the finished chip. The external terminals of the semiconductor device are configured such that they are programmed via enable signals to serve as input/output terminals of the test signals, keeping the number of the external terminals of the semiconductor device from increasing for the testing purpose.
96 Citations
10 Claims
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1. A test circuit for a plurality of monitor test element groups (TEGs), which are formed on a semiconductor chip together with a semiconductor device and placed in selected positions scattered in the chip, wherein the test circuit selectively tests the monitor TEGs to thereby monitor variations in process parameters within the chip, the test circuit comprising:
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a TEG control circuit responsive to externally applied test signals T0 and T1 to Tn for outputting control signals G1 to Gn to control the monitor TEGs, respectively; and
at least one data output terminal of the semiconductor device which is diverted by an enable signal to an input terminal for one of the test signals T0 to Tn, wherein the at least one data output terminal of the semiconductor device is connected to an input of the TEG control circuit. - View Dependent Claims (2)
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3. A test circuit for n, where n is an integer greater than one, monitor test element groups (TEGs), which are formed on the same chip as a semiconductor device is formed and placed in selected positions in the chip, wherein the test circuit selectively tests the monitor TEGs to thereby monitor variations in process parameters within the chip and each of the monitor TEGs consists of a ring oscillator, the test circuit comprising:
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a TEG control circuit responsive to externally applied test signals T0 and T1 to Tn for outputting control signals G1 to Gn to control the number n of monitor TEGs, respectively;
an n-input NOR gate or n-input OR gate responsive to outputs A1 to An of the monitor TBGs for outputting one of the outputs A1 to An of the monitor TEGs;
at least one data output terminal of the semiconductor device which is diverted by an enable signal to an input terminal for one of the test signals T0 to Tn; and
a data output terminal of the semiconductor device which is diverted by an enable signal to an output terminal for the output of the n-input NOR or OR gate, wherein the at least one data output terminal of the semiconductor device is connected to an input of the TEG control circuit, outputs of the TEG control circuit for outputting the control signals G1 to Gn are connected to the inputs of the monitor TEGs, respectively, and the output of the n-input NOR or OR gate is connected to the data output terminal of the semiconductor device. - View Dependent Claims (4, 5, 6)
the n two-input NAND gates provide a respective one of the control signals G1 to Gn.
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7. A test circuit for n, where n is an integer greater than one, monitor test element groups (TEGs), which are formed on the same chip as a semiconductor device is formed and placed in selected positions in the chip, wherein the test circuit selectively tests the monitor TEGs to thereby monitor variations in process parameters within the chip and each of the monitor TEGs consists of three-terminal elements having first, second and third terminals, the test circuit comprising:
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a TEG control circuit responsive to externally applied test signals T0 and T1 to Tn for outputting control signals G1 to Gn to control the n number of monitor TEGs, respectively;
a first external terminal for inputting first input data to the semiconductor device via a buffer circuit;
a second external terminal for inputting second input data to the semiconductor device via a buffer circuit; and
at least one data output terminal of the semiconductor device which is diverted by an enable signal to an input terminal for one of the test signals T0 and T1 to Tn, wherein the at least one data output terminal of the semiconductor device is connected to an input of the TEG control circuit, and the three-terminal element in each of the monitor TEGs has the first terminal thereof connected to the first external terminal, the second terminal thereof connected to the second external terminal and the third terminal thereof connected to receive a corresponding one of the control signals G1 to Gn from the TEG control circuit. - View Dependent Claims (8, 9, 10)
each of the partial circuits has a first input connected to receive the test signal T0 at the source of the corresponding first MOS transistor, a second input connected to receive a respective one of the test signals T1 to Tn at the input of the corresponding inverter, and an output connected in common to the drains of the corresponding first and second MOS transistors for providing a corresponding one of the output signals G1 to Gn, and the second MOS transistor has a gate thereof connected to the output of the corresponding inverter and a source thereof connected to a reference voltage.
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Specification