Cellular TDMA base station receiver with dynamic DC offset correction

• US 6,240,100 B1
• Filed: 07/31/1997
• Issued: 05/29/2001
• Est. Priority Date: 07/31/1997
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Anderson, David J., Riordan, Kenneth B., Peplinski, Neil
• Primary Examiner(s): Vu, Huy D.
• Assistant Examiner(s): BOAKYE, ALEXANDER O
• Application Number:
  US08/904,398
• Time in Patent Office: 1,398 Days
• Field of Search: 370/321, 370/337, 370/347, 370/348, 370/442, 455/324, 455/214, 455/234.2, 375/319
• US Class Current: 370/442
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04L 25/062 Setting decision thresholds using feedforward techniques only

Abstract

A receiver (10) corrects for dynamic DC offsets by utilizing an open loop predictive DC offset correction stage (18) to respond instantly to changes in AGC settings on a timeslot by timeslot basis. The receiver has an AC coupled baseband receiver and has memory (22) for storing calibration offset data (24 and 26) representing a calibration offset voltage value for each automatic gain control (AGC) state determined relative to a known reference value. The predictive DC offset stage (18) predicts a predictive DC offset correction value (74 and 76) for a selected timeslot using stored calibration offset data (24 and 26) and an average of stored calibration offset data corresponding to AGC states for all timeslots in a given frame.

Claims

1. A cellular TDMA base station receiver having an AC coupled baseband receiver with DC offset correction comprising:

storage means for storing receiver calibration offset data representing a receiver calibration offset voltage value for each automatic gain control (AGC) state determined relative to a known reference value wherein the storage means contains a table of in-phase (I) channel receiver calibration offset data representing receiver calibration offset voltage values for each automatic gain control (AGC) state determined relative to a known reference value for an in-phase signal, and also contains a table of quadrature phase (Q) channel receiver calibration offset data representing receiver calibration offset voltage values for each automatic gain control (AGC) state determined relative to a known reference value for a quadrature signal; and

means for predicting a predictive DC offset correction value for a selected timeslot using stored receiver calibration offset data corresponding to an AGC state of the selected timeslot and an average of stored calibration offset data corresponding to AGC states for all timeslots in a given frame.

2. The base station receiver of claim 1 further comprising means for providing a closed loop DC correction value on a per timeslot basis by determining a combined DC offset value consisting of a natural DC offset level and an undesired DC offset level for the selected timeslot and by determining the undesired DC offset level by averaging the combined DC offset value for the selected timeslot over a plurality of frames;

and

means for providing a composite DC offset correction value by summing the predictive DC correction value and the closed loop DC correction value on a timeslot by timeslot basis to facilitate correction for detected DC offsets.

3. The base station receiver of claim 2 wherein the means for predicting and the means for providing a closed loop DC correction value is a digital signal processor.

4. The base station receiver of claim 1 having a baseband in-phase channel mixing circuit and a baseband quadrature phase channel mixing circuit coupled to mix a local oscillator (LO) frequency from a local oscillator circuit wherein the baseband in-phase channel mixing circuit, the baseband quadrature phase channel mixing circuit and the local oscillator are located on a same integrated circuit chip.

5. The base station receiver of claim 3 wherein the receiver is a zero intermediate frequency (IF) receiver having an IF frequency of at least 167 MHz and local oscillator (LO) frequency of at least 167 MHz.

6. The base station receiver of claim 5 wherein the means for predicting accesses the table every timeslot to determine an appropriate predictive DC offset correction value based on an accessed receiver calibration offset voltage value.

7. The base station receiver of claim 1 further including means for setting AGC settings and for measuring an output of an A/D converter to determine the receiver calibration offset data representing the receiver calibration offset voltage values for each automatic gain control (AGC) state determined relative to the known reference value for storage in the storage means.

8. The base station receiver of claim 5 wherein the means for predicting the DC offset correction value is a digital signal processor that:

determines an AGC setting for each timeslot in a current frame;

retrieves the I channel receiver calibration offset data and Q channel receiver calibration offset data from the tables for each timeslot in the frame; and

subtracts the predictive DC offset correction value, which represents an undesired DC offset component, from digital I and Q baseband data prior to demodulation.

9. A cellular TDMA base station receiver having an AC coupled baseband receiver with DC offset correction comprising:

storage means for storing receiver calibration offset data representing a receiver calibration offset voltage value for each automatic gain control (AGC) state determined relative to a known reference value wherein the storage means contains a table of in-phase (I) channel receiver calibration offset data representing receiver calibration offset voltage values for each automatic gain control (AGC) state determined relative to a known reference value for an in-phase signal, and also contains a table of quadrature phase (Q) channel receiver calibration offset data representing receiver calibration offset voltage values for each automatic gain control (AGC) state determined relative to a known reference value for a quadrature signal;

means for predicting a predictive DC offset correction value for a selected timeslot using stored receiver calibration offset data corresponding to an AGC state of the selected timeslot and an average of stored calibration offset data corresponding to AGC states for all timeslots in a given frame, wherein the means for predicting the predictive DC offset correction value is a digital signal processor that;

determines an AGC setting for each timeslot in a current frame;

retrieves I channel receiver calibration offset data and Q channel receiver calibration offset data from the storage means for each timeslot in the frame; and

subtracts the predictive DC offset correction value, which represents an undesired DC offset component, from digital I and Q baseband data prior to demodulation;

means, responsive to corrected baseband information, for providing a closed loop DC correction value on a per timeslot basis by determining a combined DC offset value consisting of a natural DC offset level and an undesired DC offset level for the selected timeslot and by determining the undesired DC offset level by averaging the combined DC offset value for the selected timeslot over a plurality of frames; and

means for providing a composite offset correction value by summing the predictive DC correction value and the closed loop DC correction value on a timeslot by timeslot basis to facilitate correction for detected DC offsets.

10. The base station receiver of claim 9 having a baseband in-phase channel mixing circuit and a baseband quadrature phase channel mixing circuit coupled to mix a local oscillator (LO) frequency from a local oscillator circuit wherein the baseband in-phase channel mixing circuit, the baseband quadrature phase channel mixing circuit and the local oscillator are located on a same integrated circuit chip.