Two line variable word length serial interface

• US 6,240,193 B1
• Filed: 09/17/1998
• Issued: 05/29/2001
• Est. Priority Date: 09/17/1998
• Status: Expired due to Term

• Current Assignee: Sonic Innovations Incorporated (William Demant Fonden)
• Original Assignee: Sonic Innovations Incorporated (William Demant Fonden)
• Inventors: Green, Robert Sherman
• Primary Examiner(s): Le, Huyen
• Assistant Examiner(s): DABNEY, PHYLESHA LARVINIA
• Application Number:
  US09/156,546
• Time in Patent Office: 985 Days
• Field of Search: 381/312, 381/314, 381/315, 381/323, 710/129, 710/130, 710/69
• US Class Current: 381/314
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: H04R 25/558 Remote control, e.g. of amplification, frequency

Abstract

In a serial interface for a programmable hearing aid, no address is provided for the data transferred to or read from the hearing aid, rather, for each instruction, the number of data words being transferred pursuant to each instruction and the beginning word are known in the controlled device. In the serial interface, the data is clocked into and out of the hearing aid on a serial data pin by a serial clock. Because no addresses are sent along with the data to the controlled device, the amount of data transferred to the hearing aid is significantly reduced, and no circuitry is required to save the address.

Claims

1. A serial interface for a programmable hearing aid comprising:

a serial clock pin connected to a command register, a control register, a first two-input multiplexer, and a second two-input multiplexer, wherein said serial clock pin is used to input a serial clock that clocks in read and write instructions from a serial data stream;

a serial data pin connected to an input of an input buffer and to an output of an output buffer, wherein said serial data pin is employed to input said serial data stream, said input buffer being connected to a first plurality of registers and said output buffer being connected to a second plurality of registers,

a power pin connected to an input of an analog-to-digital converter, wherein an output of said analog-to-digital converter is connected to an analog-to-digital converter register; and

a ground pin.

2. The serial interface of claim 1 wherein said first plurality of registers includes a gain register, an analog-to-digital converter register, a register file input buffer register, a volume control register, an EEPROM input buffer register, a digital signal processor output register, a temporary trim register, a command register, and a control register.

3. The serial interface of claim 2 wherein said second plurality of registers includes said analog-to-digital converter register, a register file output buffer register, an EEPROM output buffer register, and said digital signal processor output register.

4. The serial interface of claim 3 wherein a second input of said first two-input multiplexer is connected to an internal oscillator that also provides a clock to said analog-to-digital converter, an output of said analog-to-digital converter being connected to said analog-to-digital converter register, an output of said first multiplexer being connected to the input of a divide-by-four circuit, the output of said divide-by-four circuit being connected to a second input of said second two-input multiplexer, an output of said second two-input multiplexer providing said clock to a digital signal processor.

5. The serial interface of claim 4 wherein an output of said register file input buffer register is connected to a register file, an output of said register file being connected to an input of said register file output buffer register, an output of said digital signal processor output register being connected to said digital-to-analog converter.

6. The serial interface of claim 5 wherein an output of said EEPROM input buffer register is connected to an EEPROM, an output of said EEPROM being connected to an input of said EEPROM output register and a trim latch, said output of trim latch being connected to a first input of a third two-input multiplexer, a second input of said third two-input multiplexer being connected to an output of a temporary trim register, an output of said third two-input multiplexer providing trim signals to various circuits in the programmable hearing aid.