High-speed broadband wireless communication system architecture

• US 6,240,274 B1
• Filed: 04/21/1999
• Issued: 05/29/2001
• Est. Priority Date: 04/21/1999
• Status: Expired due to Fees

• Current Assignee: HRL Laboratories LLC (The Boeing Co.)
• Original Assignee: HRL Laboratories LLC (The Boeing Co.)
• Inventors: Izadpanah, Hossein
• Primary Examiner(s): Chang, Vivian
• Assistant Examiner(s): APPIAH, CHARLES NANA
• Application Number:
  US09/295,705
• Time in Patent Office: 769 Days
• Field of Search: 455/42.2, 455/39, 370/345, 370/350, 370/536, 370/535, 370/416, 370/913
• US Class Current: 455/39
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04W 56/00 Synchronisation arrangements
• CPC Class Codes: Y10S 370/913 Wireless or radio
• CPC Class Codes: Y10S 370/916 Multiplexer/demultiplexer

Abstract

Techniques and architecture as well as channel multiplexing schemes to design and implement multi-megabit and gigabit transfer of data in situations requiring or optimized by wireless communication systems are presented as a method by which the high-speed signal integrity of a transmission may be maintained over a hostile wireless link and by which a high-speed transmission may be made while maintaining a bit-rate below the delay spread value such that the unforgiving propagation conditions normally associated with high-speed transfer are mitigated. The system is adaptable to any use where a multi-megabit and gigabit wireless link is desirable; for example in office buildings lacking fiber infrastructure, in rapid deployment situations such as those required in military or emergency situations, or where other separate broadband infrastructures do not exist to the end users for integrated telephone, Internet, and digital data systems.

Claims

1. A broadband wireless communication system architecture including:

a. at least one transmitting portion configured to receive a digital multiplexed serial signal from a high bit-rate data transfer means, said transmitting portions including;

i. a transmitting portion master clock having a transmitting portion master clock frequency;

ii. a transmitting portion frequency divider connected to the transmitting portion master clock to divide the transmitting portion master clock frequency by an integer number N to provide an N-divided transmitting portion master clock frequency;

iii. a transmitting portion local oscillator having a transmitting portion local oscillator frequency;

iv. a transmitting portion harmonic generator connected to the transmitting portion local oscillator to multiply the transmitting portion local oscillator frequency by an N-member series of harmonics H_i to generate an N-member set of H_i-multiplied carrier frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

v. a demultiplexer connected to the transmitting portion master clock to receive the transmitting portion master clock frequency therefrom, the demultiplexer controlled by the transmitting portion master clock frequency to demultiplex a received digital multiplexed serial signal into a plurality of N-digital parallel sub-rate channels and to add a digital header to each of the N-digital parallel sub-rate channels, the digital header including channel number, sequence, and synchronization information with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

vi. a plurality N of transmitting portion modems connected to the N-way demultiplexer, each transmitting portion modem positioned to receive one of the N-digital parallel sub-rate channels therefrom, the plurality N of transmitting portion modems further connected to the transmitting portion frequency divider to receive the N-divided transmitting portion master clock frequency therefrom with the N-divided transmitting portion master clock frequency synchronizing the operation of the plurality N of the transmitting portion modems, the plurality N of transmitting portion modems further connected to the transmitting portion harmonic generator with each transmitting portion modem positioned to receive one of the series of H_i-multiplied carrier frequencies therefrom with the N-digital parallel sub-rate channels, the N-divided transmitting portion master clock frequency, and the H_i-multiplied carrier frequencies acting substantially simultaneously on the plurality of transmitting portion modems to convert the N-digital parallel sub-rate channels into N-analog parallel channels, each of the N-analog parallel channels synchronized with the other N-analog parallel channels by the N-divided transmitting portion master clock frequency and modulated onto one of the series of H_i-multiplied carrier frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

vii. a transmitting portion combiner connected to the plurality N of transmitting portion modems to receive the N-analog parallel channels and to combine them into a combined analog signal;

viii. a transmitting portion up-converter, connected to the transmitting portion combiner to receive the combined analog signal and to convert the combined analog signal into a higher frequency combined analog signal;

ix. a transmitting portion amplifier connected to the transmitting portion up-converter to receive the higher frequency analog combined analog signal to increase the power of the higher frequency combined analog signal and;

x. a transmitting antenna, connected to the transmitting portion amplifier to receive and broadcast the amplified higher frequency signal as a radio transmission;

b. at least one receiving portion configured to send a digital multiplexed serial signal into a high bit-rate data transfer means including;

i. a receiving antenna positioned to receive a radio transmission as a higher frequency signal;

ii. a receiving portion amplifier connected to the receiving antenna to receive and increase the power of the higher frequency signal;

iii. a down-converter connected to the receiving portion amplifier to receive the amplified higher frequency signal and to convert it into a lower frequency signal;

iv. a N-way splitter connected to the down-converter to receive the lower frequency signal and to split it in a plurality N-ways into a plurality N-lower frequency signals with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

v. a plurality N of frequency filters, each of the frequency filters connected to the splitter to receive an individual lower frequency signal from the plurality N-lower frequency signals and to filter the received individual lower frequency signal for a desired channel frequency selected from the individual H_i-multiplied carrier frequencies of the transmitting portion, the plurality N of frequency filters chosen to provide filtration of the plurality of N-lower frequency signals into the original series of N-analog parallel channels with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

vi. a receiving portion master clock having a receiving portion master clock frequency equal to the transmitting portion master clock frequency;

vii. a divider connected to the receiving portion master clock to divide the receiving portion master clock frequency by an integer number N to provide an N-divided receiving portion master clock frequency, with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

viii. a receiving portion local oscillator having a receiving portion local oscillator frequency equal to the transmitting portion local oscillator frequency;

ix. a receiving portion harmonic generator connected to the receiving portion local oscillator to multiply the local oscillator frequency by a series of harmonics H_i to generate an N-member series H_i of equally spaced H_i-multiplied carrier frequencies equal to the equally spaced H_i-multiplied carrier frequencies generated in the transmitting portion harmonic generator with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

x. a plurality N of receiving portion modems connected to the plurality N of frequency filters, each receiving portion modem positioned to receive one of the N-lower frequency signals from an individual frequency filter, the plurality N of receiving portion modems further connected to the N-way divider to receive the N-divided receiving portion master clock frequency therefrom with the N-divided receiving portion master clock frequency synchronizing the operation of the plurality N of receiving portion modems, the plurality N of receiving portion modems further connected to the receiving portion harmonic generator with each receiving portion modem positioned to receive one of the series of H_i-multiplied carrier frequencies therefrom, the N-lower frequency signals, the N-divided receiving portion master clock frequency, and the H_i-multiplied carrier frequencies acting substantially simultaneously on the plurality N of receiving portion modems to convert the N-lower frequency analog signals into N-digital parallel sub-rate channels, each of the N-digital parallel sub-rate channels synchronized with the other N-digital parallel sub-rate channels by the N-divided receiving portion master clock frequency and demodulated using one of the series of H_i×

N-multiplied carrier frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency and;

xi. a N-way multiplexer connected to receive the N-digital parallel sub-rate channels from the plurality of modems, the N-way multiplexer further connected to the receiving portion master clock to receive the receiving portion master clock frequency as a control signal therefrom to be used with the digital sub-rate header added by the demultiplexer of the transmitting portion to control the multiplexing of the received N-digital parallel sub-rate channels to generate a digital multiplexed serial signal, the digital multiplexed serial signal being identical to the digital multiplexed serial received in the transmitting portion from the high bit-rate data transfer means with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency.

2. A broadband wireless communication system architecture as set forth in claim 1, wherein the transmitting portion amplifier individually amplifies each of the modulated carrier frequencies with a frequency-related gain which increases with the modulated carrier frequency to minimize the frequency-related unequal propagation losses occurring at the individual sub-carrier frequencies.

3. A broadband wireless communication system architecture as set forth in claim 1, wherein the one or more members of the H_i-multiplied carrier frequencies may be utilized to provide variations in the allocation of transmission bandwidth between the transmitting portions and the receiving portions, whereby different users of the transmitting and receiving portions may be allocated varying bandwidth depending on their specific needs.

4. A broadband wireless communication system architecture as set forth in claim 1, wherein the transmitting portion amplifier individually amplifies each of the modulated carrier frequencies with a frequency-related gain which increases with the modulated carrier frequency to minimize the frequency-related unequal propagation losses occurring at the individual sub-carrier frequencies.

5. A broadband wireless communication system architecture as set forth in claim 1, wherein the one or more members of the H_i-multiplied carrier frequencies may be utilized to provide variations in the allocation of transmission bandwidth between the transmitting portions and the receiving portions, whereby different users of the transmitting and receiving portions may be allocated varying bandwidth depending on their specific needs.

6. A broadband wireless communication system architecture including:

a. at least one transmitting portion configured to receive a digital multiplexed serial signal from a high bit-rate data transfer means, said transmitting portions including;

i. a transmitting portion master clock having a transmitting portion master clock frequency;

ii. a transmitting portion frequency divider connected to the transmitting portion master clock to divide the transmitting portion master clock frequency by an integer number N to provide an N-divided transmitting portion master clock frequency;

iii. a transmitting portion local oscillator having a transmitting portion local oscillator frequency;

iv. a transmitting portion harmonic generator connected to the transmitting portion local oscillator to multiply the transmitting portion local oscillator frequency by an N-member series of harmonics H_i to generate an N-member set of H_i-multiplied carrier frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

v. a demultiplexer connected to the transmitting portion master clock to receive the transmitting portion master clock frequency therefrom, the demultiplexer controlled by the transmitting portion master clock frequency to demultiplex a received digital multiplexed serial signal into a plurality of N-digital parallel sub-rate channels and to add a digital header to each of the N-digital parallel sub-rate channels, the digital header including channel number, sequence, and synchronization information with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

vi. a plurality N of transmitting portion modems connected to the N-way demultiplexer, each transmitting portion modem positioned to receive one of the N-digital parallel sub-rate channels therefrom, the plurality N of transmitting portion modems further connected to the transmitting portion frequency divider to receive the N-divided transmitting portion master clock frequency therefrom with the N-divided transmitting portion master clock frequency synchronizing the operation of the plurality N of the transmitting portion modems, the plurality N of transmitting portion modems further connected to the transmitting portion harmonic generator with each transmitting portion modem positioned to receive one of the series of H_i-multiplied carrier frequencies therefrom with the N-digital parallel sub-rate channels, the N-divided transmitting portion master clock frequency, and the H_i-multiplied carrier frequencies acting substantially simultaneously on the plurality of transmitting portion modems to convert the N-digital parallel sub-rate channels into N-analog parallel channels, each of the N-analog parallel channels synchronized with the other N-analog parallel channels by the N-divided transmitting portion master clock frequency and modulated onto one of the series of H_i-multiplied carrier frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

vii. a plurality N of transmitting portion up-converters, each of the plurality N of transmitting portion up-converters connected to one of the plurality N of transmitting portion modems to receive the N-analog parallel channels and to convert the N-analog parallel channels to higher frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

viii. a plurality N of transmitting portion amplifiers, each of the plurality N of transmitting portion amplifiers connected to one of the plurality N of transmitting portion up-converters to receive the higher frequency N-analog parallel channels and to increase the power of the higher frequency N-analog parallel channels with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

ix. a plurality N of transmitting antennas, each of the plurality N of transmitting antennas connected to one of the plurality N of transmitting portion amplifiers to receive the amplified higher frequency N-analog parallel channels and broadcast the amplified higher frequency signal as a radio transmission with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

b. at least one receiving portion configured to send a digital multiplexed serial signal into a high bit-rate data transfer means including;

i. a receiving antenna positioned to receive a radio transmission as a higher frequency signal;

ii. a receiving portion amplifier connected to the receiving antenna to receive and increase the power of the higher frequency signal;

iii. a down-converter connected to the receiving portion amplifier to receive the amplified higher frequency signal and to convert it into a lower frequency signal;

iv. a N-way splitter connected to the down-converter to receive the lower frequency signal and to split it in a plurality N-ways into a plurality N-lower frequency signals with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

v. a plurality N of frequency filters, each of the frequency filters connected to the splitter to receive an individual lower frequency signal from the plurality N-lower frequency signals and to filter the received individual lower frequency signal for a desired channel frequency selected from the individual H_i-multiplied carrier frequencies of the transmitting portion, the plurality N of frequency filters chosen to provide filtration of the plurality of N-lower frequency signals into the original series of N-analog parallel channels with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

vi. a receiving portion master clock having a receiving portion master clock frequency equal to the transmitting portion master clock frequency;

vii. a divider connected to the receiving portion master clock to divide the receiving portion master clock frequency by an integer number N to provide an N-divided receiving portion master clock frequency, with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

viii. a receiving portion local oscillator having a receiving portion local oscillator frequency equal to the transig portion local oscillator frequency;

ix. a receiving portion harmonic generator connected to the receiving portion local oscillator to multiply the local oscillator frequency by a series of harmonics H_i to generate an N-member series H_i of equally spaced H_i-multiplied carrier frequencies equal to the equally spaced Hi-multiplied carrier frequencies generated in the transmitting portion harmonic generator with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

x. a plurality N of receiving portion modems connected to the plurality N of frequency filters, each receiving portion modem positioned to receive one of the N-lower frequency signals from an individual frequency filter, the plurality N of receiving portion modems further connected to the N-way divider to receive the N-divided receiving portion master clock frequency therefrom with the N-divided receiving portion master clock frequency synchronizing the operation of the plurality N of receiving portion modems, the plurality N of receiving portion modems further connected to the receiving portion harmonic generator with each receiving portion modem positioned to receive one of the series of H_i-multiplied carrier frequencies therefrom, the N-lower frequency signals, the N-divided receiving portion master clock frequency, and the H_i-multiplied carrier frequencies acting substantially simultaneously on the plurality N of receiving portion modems to convert the N-lower frequency signals into N-digital parallel sub-rate channels, each of the N-digital parallel sub-rate channels synchronized with the other N-digital parallel sub-rate channels by the N-divided receiving portion master clock frequency and demodulated using one of the series of H_i×

N-multiplied carrier frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency and;

xi. a N-way multiplexer connected to receive the N-digital parallel sub-rate channels from the plurality of modems, the N-way multiplexer further connected to the receiving portion master clock to receive the receiving portion master clock frequency as a control signal therefrom to be used with the digital sub-rate header added by the demultiplexer of the transmitting portion to control the multiplexing of the received N-digital parallel sub-rate channels to generate a digital multiplexed serial signal, the digital multiplexed serial signal being identical to the digital multiplexed serial received in the transmitting portion from the high bit-rate data transfer means with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency.

7. A broadband wireless communication system architecture as set forth in claim 6, wherein the transmitting portion amplifier individually amplifies each of the modulated carrier frequencies with a frequency-related gain which increases with the modulated carrier frequency to minimize the frequency-related unequal propagation losses occurring at the individual sub-carrier frequencies.

8. A broadband wireless communication system architecture as set forth in claim 6, wherein the one or more members of the H_i-multiplied carrier frequencies may be utilized to provide variations in the allocation of transmission bandwidth between the transmitting portions and the receiving portions, whereby different users of the transmitting and receiving portions may be allocated varying bandwidth depending on their specific needs.

9. A broadband wireless communication system architecture including:

a. at least one transmitting portion configured to receive a digital multiplexed serial signal from a high bit-rate data transfer means, said transmitting portions including;

i. a transmitting portion master clock having a transmitting portion master clock frequency;

ii. a transmitting portion frequency divider connected to the transmitting portion master clock to divide the transmitting portion master clock frequency by an integer number N to provide an N-divided transmitting portion master clock frequency;

iii. a transmitting portion local oscillator having a transmitting portion local oscillator frequency;

iv. a transmitting portion harmonic generator connected to the transmitting portion local oscillator to multiply the transmitting portion local oscillator frequency by an N-member series of harmonics H_i to generate an N-member set of H_i-multiplied carrier frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

v. a demultiplexer connected to the transmitting portion master clock to receive the transmitting portion master clock frequency therefrom, the demultiplexer controlled by the transmitting portion master clock frequency to demultiplex a received digital multiplexed serial signal into a plurality of N-digital parallel sub-rate channels and to add a digital header to each of the N-digital parallel sub-rate channels, the digital header including channel number, sequence, and synchronization information with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

vi. a plurality N of transmitting portion modems connected to the N-way demultiplexer, each transmitting portion modem positioned to receive one of the N-digital parallel sub-rate channels therefrom, the plurality N of transmitting portion modems further connected to the transmitting portion frequency divider to receive the N-divided transmitting portion master clock frequency therefrom with the N-divided transmitting portion master clock frequency synchronizing the operation of the plurality N of the transmitting portion modems, the plurality N of transmitting portion modems further connected to the transmitting portion harmonic generator with each transmitting portion modem positioned to receive one of the series of H_i-multiplied carrier frequencies therefrom with the N-digital parallel sub-rate channels, the N-divided transmitting portion master clock frequency, and the H_i-multiplied carrier frequencies acting substantially simultaneously on the plurality of transmitting portion modems to convert the N-digital parallel sub-rate channels into N-analog parallel channels, each of the N-analog parallel channels synchronized with the other N-analog parallel channels by the N-divided transmitting portion master clock frequency and modulated onto one of the series of H_i-multiplied carrier frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

vii. a plurality N of transmitting portion up-converters, each of the plurality N of transmitting portion up-converters connected to one of the plurality N of transmitting portion modems to receive the N-analog parallel channels and to convert the N-analog parallel channels to higher frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

viii. a plurality N of transmitting portion amplifiers, each of the plurality N of transmitting portion amplifiers connected to one of the plurality N of transmitting portion up-converters to receive the higher frequency N-analog parallel channels and to increase the power of the higher frequency N-analog parallel channels with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

ix. a plurality N of transmitting antennas, each of the plurality N of transmitting antennas connected to one of the plurality N of transmitting portion amplifiers to receive the amplified higher frequency N-analog parallel channels and broadcast the amplified higher frequency signal as a radio transmission with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

b. at least one receiving portion configured to send a digital multiplexed serial signal into a high bit-rate data transfer means including;

i. a plurality N of receiving antennas positioned to receive a radio transmission as a higher frequency signal with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

ii. a plurality N of receiving portion amplifiers, each of the plurality N of receiving portion amplifiers connected to one of the plurality N of receiving antennas to receive and increase the power of the higher frequency signal with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

iii. a plurality N of down-converters, each of the plurality N of down-converters connected to one of the plurality N of receiving portion amplifiers to receive the amplified higher frequency signals and to convert them into lower frequency signals with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

iv. a plurality N of frequency flters, each of the frequency filters connected to one of the plurality of N down-converters to receive an individual lower frequency signal and to filter the received individual lower frequency signal for a desired channel frequency selected from the individual H_i-multiplied carrier frequencies of the transmitting portion, the plurality N of frequency filters chosen to provide filtration of the plurality of N-lower frequency signals into the original series of N-analog parallel channels with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

v. a receiving portion master clock having a receiving portion master clock frequency equal to the transmitting portion master clock frequency;

vi. a divider connected to the receiving portion master clock to divide the receiving portion master clock frequency by an integer number N to provide an N-divided receiving portion master clock frequency, with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

vii. a receiving portion local oscillator having a receiving portion local oscillator frequency equal to the transmitting portion local oscillator frequency;

viii. a receiving portion harmonic generator connected to the receiving portion local oscillator to multiply the local oscillator frequency by a series of harmonics H_i to generate an N-member series H_i of equally spaced H_i-multiplied carrier frequencies equal to the equally spaced H_i-multiplied carrier frequencies generated in the transmitting portion harmonic generator with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency;

ix. a plurality N of receiving portion modems connected to the plurality N of frequency filters, each receiving portion modem positioned to receive one of the N-lower frequency signals from an individual frequency filter, the plurality N of receiving portion modems further connected to the N-way divider to receive the N-divided receiving portion master clock frequency therefrom with the N-divided receiving portion master clock frequency synchronizing the operation of the plurality N of receiving portion modems, the plurality N of receiving portion modems firther connected to the receiving portion harmonic generator with each receiving portion modem positioned to receive one of the series of H_i-multiplied carrier frequencies therefrom, the N-lower frequency signals, the N-divided receiving portion master clock frequency, and the H_i-multiplied carrier frequencies acting substantially simultaneously on the plurality N of receiving portion modems to convert the N-lower frequency signals into N-digital parallel sub-rate channels, each of the N-digital parallel sub-rate channels synchronized with the other N-digital parallel sub-rate channels by the N-divided receiving portion master clock frequency and demodulated using one of the series of H_i×

N-multiplied carrier frequencies with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency and;

x. a N-way multiplexer connected to receive the N-digital parallel sub-rate channels from the plurality of modems, the N-way multiplexer further connected to the receiving portion master clock to receive the receiving portion master clock frequency as a control signal therefrom to be used with the digital sub-rate header added by the demultiplexer of the transmitting portion to control the multiplexing of the received N-digital parallel sub-rate channels to generate a digital multiplexed serial signal, the digital multiplexed serial signal being identical to the digital multiplexed serial received in the transmitting portion from the high bi-trate data transfer means with N selected as equal to the integer number N used in the transmitting portion frequency divider to provide the N-divided transmitting portion master clock frequency.