Data transfer interfacing

• US 6,240,471 B1
• Filed: 09/10/1996
• Issued: 05/29/2001
• Est. Priority Date: 09/10/1996
• Status: Expired due to Term

• Current Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Original Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Inventors: Linderman, Mark H., Schlueter, Erick A., Linderman, Richard W.
• Primary Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US08/716,914
• Time in Patent Office: 1,722 Days
• Field of Search: 395/882, 395/883, 395/884, 395/885, 395/873, 395/877, 710/62
• US Class Current: 710/62
• CPC Class Codes: H04Q 11/0421 Circuit arrangements therefor
• CPC Class Codes: H04Q 2213/13003 Constructional details of switching devices
• CPC Class Codes: H04Q 2213/1301 Optical transmission, optical switches
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/13106 Microprocessor, CPU
• CPC Class Codes: H04Q 2213/13204 Protocols
• CPC Class Codes: H04Q 2213/13305 Transistors, semiconductors in general
• CPC Class Codes: H04Q 2213/1332 Logic circuits

Abstract

A single Printed Circuit Board (PCB) designed to acquire data from a multiplicity of heterogeneous sources and convert the data to a high performance protocol suitable for transmission over long distances via fiber optic lines. A specific embodiment uses the Fiber Channel protocol on fiber optic cables to carry information between sensors and high performance computers (HPC). The High Performance Parallel Interface (HiPPI) is used as the protocol to connect to the HPC. Simplex (unidirectional) and full duplex communications are supported.

Claims

1. Apparatus for interconnecting a first medium having a prescribed interface and a second medium having a hardware interface reconfigurable at gate level;

said hardware interface being effective, through reconfiguring, to implement a variety of interface specifications effective for communicating information trough said second medium;

said prescribed interface implementing a specification effective for communicating information through said first medium;

said hardware interface being a one of;

(1) asynchronous with respect to said prescribed interface,

(2) strobed with no continuous clock present, and

(3) synchronous with respect to said prescribed interface in a manner undetermined at reconfiguration; and

said apparatus comprising said prescribed interface, said hardware interface, and means for connecting said prescribed interface and said hardware interface.

2. Apparatus as defined in claim 1 wherein each of said first and said second medium is compatible with a one of fiber optic cable, wire, and wireless media.

3. Apparatus as defined in claim 1 wherein said prescribed interface specification is High Performance Parallel Interface (HIPPI) or fiber channel.

4. Apparatus as defined in claim 1 wherein each of said first and said second medium supports bidirectional communications and feedback.

5. Apparatus as defined in claim 1, wherein said means for connecting includes a transceiver connected to said hardware interface.

6. Apparatus as defined in claim 1, wherein two implementations of said apparatus for interconnecting communicate over said prescribed interface.

7. Apparatus as defined in claim 1, wherein said hardware interface includes a field programmable gate array (FPGA).

8. Apparatus as defined in claim 7 wherein received information is communicated through a one of said first and said second medium and transmitted information is communicated through another of said first and said second medium;

said received information differs from said transmitted information; and

conversion between said received and said transmitted information is performed by said FPGA.

9. Apparatus as defined in claim 8 wherein said transmitted information is derived from said received information.

10. Apparatus as defined in claim 8 wherein said transmitted information includes information not derived from said received information.