Bus bridge that provides selection of optimum timing speed for transactions

• US 6,240,480 B1
• Filed: 05/07/1998
• Issued: 05/29/2001
• Est. Priority Date: 05/07/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.), Pumpkin Limited (Rauch Acquisition Corp.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Knecht, Mark, Wong, Jacques, Waldron, Scott
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/074,578
• Time in Patent Office: 1,118 Days
• Field of Search: 710/128, 710/129, 710/126, 710/112, 710/118, 710/5, 710/2, 710/10, 710/25, 710/101, 710/60, 710/107, 710/1, 710/4, 710/26, 710/62, 710/127, 711/100, 711/143, 713/501, 713/500, 713/600, 709/28
• US Class Current: 710/311
• CPC Class Codes: G06F 13/404 with address mapping

Abstract

An improved bus bridge in a computer system for connecting a first data bus and a second data bus, said bus bridge having means for connecting said first and second buses, means for receiving an address representing a transaction on said first bus, means for decoding said address, means for claiming the transaction on said first bus corresponding to said address, and means for passing said transaction to said second bus, wherein the improvement comprises: (a) means for determining if said address decodes into one of a plurality of address ranges programmed in said bridge device; (b) means for determining a timing speed for the transaction corresponding to said address in accordance with the address range for said address; and (d) means for asserting a signal for claiming the transaction at said determined timing speed.

Claims

1. A computer method for efficient claiming of transactions on a computer data bus by a bus bridge device having programmable timing speed for claiming the transactions, comprising the steps of:

receiving an address representing a transaction on said data bus;

decoding said address into one of a plurality of address ranges programmed in said bridge device, at least one of said plurality of address ranges corresponds to a legacy device address range assigned for legacy devices;

determining if the decoded address is in the legacy device address range corresponding to a legacy device,

determining if the legacy device address range for the legacy device is enabled;

determining a timing speed for the transaction corresponding to said decoded address in accordance with the legacy device address range if the legacy device address range is enabled; and

asserting a signal for claiming the transaction at said determined timing speed.

2. A computer method as recited in claim 1 further including the steps of:

determining if an aliasing function is enabled; and

using 32-bit decoding for decoding said address if said aliasing function is enabled.

3. A computer method as recited in claim 1 wherein said bus bridge device has one or more registers for programming said timing speeds and for providing for said legacy devices.

4. A computer method as recited in claim 1 wherein said bus bridge device has a programmable device-select register for indicating timing speeds for said plurality of address ranges.

5. A computer method as recited in claim 4 wherein said plurality of address ranges include memory address ranges.

6. A computer method as recited in claim 1 wherein said bus bridge device has a programmable legacy device support register for indicating enabling of support for the respective legacy devices.

7. A computer method as recited in claim 2 wherein said bus bridge device has an aliasing enable register for indicating enabling of 32-bit address decoding.

8. An improved bus bridge in a computer system for connecting a first data bus and a second data bus, said bus bridge having means for connecting said first and second buses, means for receiving an address representing a transaction on said first bus, means for decoding said address, means for claiming the transaction on said first bus corresponding to said address, and means for passing said transaction to said second bus,

wherein the improvement comprises:

means for determining if said address decodes into one of a plurality of address ranges programmed in said bridge device, at least one of said plurality of address ranges corresponds to a legacy device address range assigned for legacy devices;

means for determining if the decoded address is in the legacy device address range corresponding to a legacy device,

means for determining if the legacy device address range for the legacy device is enabled;

means for determining a timing speed for the transaction corresponding to said decoded address in accordance with the legacy device address range if the legacy device address range is enabled; and

means for asserting a signal for claiming the transaction at said determined timing speed.

9. An improved bus bridge as recited in claim 8 further including:

means for determining if a predefined aliasing function is enabled; and

means for using 32-bit decoding for decoding said address if said aliasing function is enabled.

10. An improved bus bridge as recited in claim 8 further including one or more registers for programming said timing speeds and for providing for said legacy devices.

11. An improved bus bridge as recited in claim 8 further including a programmable device-select register for indicating timing speeds for said plurality of address ranges.

12. An improved bus bridge as recited in claim 11 wherein said plurality of address ranges include memory address ranges.

13. An improved bus bridge as recited in claim 8 further including a programmable legacy device support register for indicating enabling of support for the respective legacy devices.

14. An improved bus bridge as recited in claim 9 further including an aliasing enable register for indicating enabling of 32-bit address decoding.