Prefetching hints

• US 6,240,488 B1
• Filed: 12/01/1997
• Issued: 05/29/2001
• Est. Priority Date: 03/24/1995
• Status: Expired due to Term

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Mowry, Todd C.
• Primary Examiner(s): SAX, STEVEN PAUL
• Application Number:
  US08/982,244
• Time in Patent Office: 1,275 Days
• Field of Search: 345/326, 345/101, 345/114, 345/115, 345/116, 345/111, 345/110, 345/728, 345/338, 345/501, 345/502, 345/503, 345/504, 345/505, 345/506, 345/520-521 , 345/522-526, 345/203
• US Class Current: 711/128
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for refill operations, and a second portion which identifies a destination.

Claims

1. In a processor with an n-way, set associative cache, a method comprising:

addressing the cache using address information contained in an instruction, said instruction including a hint field;

indicating a cache miss for desired data that is addressed by said instruction;

specifying a refill destination for said desired data with a first portion of said hint field, wherein said destination is a first way in said cache when said desired data is a first type of data and a second way in said cache when said desired data is a second type of data, said first portion being operable in subsequent instructions to consistently specify such way destinations for subsequent first and second types of data; and

refilling said cache with said desired data.

2. The method of claim 1 further comprising the step of enabling said specifying step using a second portion of said hint field.

3. The method of claim 2 wherein said refilling step refills said first way of said cache and further comprising a third portion of said hint field which indicates whether said desired data is expected to be modified.

4. The method of claim 1 further comprising the step of disabling said specifying step using a second portion of said hint field.

5. The method of claim 4 further comprising the step of refilling said cache based on a least-recently-used protocol.

14. The method of claim 1 wherein said first type of data and said second type of data are streamed data and retained data, respectively.

6. A processor comprising:

a first n-way, set associative cache containing a first-cache line that is addressed using address information contained in an instruction, said instruction also containing a hint field;

a first comparator, coupled to said first n-way cache, for indicating a first-cache miss when said first-cache line is addressed and does not contain desired data; and

a first multiplexer, coupled to said first n-way cache, for choosing a first destination indicator used to direct refilling of said first-cache line with said desired data, said first destination indicator being chosen from a first portion of said hint field and a first alternative indicator, said first portion specifying a first way for desired data identified as a first data type and a second way for desired data identified as a second data type, and said first alternative indicator specifying a destination way for desired data without regard to data type, said first portion being operable in subsequent refill operations to consistently specify first and second way destinations for subsequent first data type and second data type data, respectively.

7. The processor of claim 6 further comprising a means for disabling a refill operation of said cache line when said first way is unavailable.

8. The processor of claim 6 further comprising:

a second n-way cache, coupled to said first cache, containing a second cache line that is addressed using said address information;

a second comparator, coupled to said second cache, for indicating a second-cache miss when said second cache line is addressed; and

a second multiplexer, coupled to said second cache, for choosing a second destination indicator used to direct refilling of said second cache line with said desired data, said second destination indicator being chosen from said first portion of said hint field and a second alternative indicator, said first portion being operable to consistently specify said first way for desired data identified as first data type and said second way for desired data identified as second data type, and said second alternative indicator specifying a destination way for desired data without regard to data type.

15. The processor of claim 6 wherein said hint field includes a second portion which controls said first multiplexer.

16. The processor of claim 6 wherein said first data type and said second data type are streamed data and retained data, respectively.

19. The processor of claim 6 wherein said first alternative indicator is an LRU bit.

20. The processor of claim 6 wherein said first alternative indicator is a randomly generated bit.

9. A processor comprising:

a queue for holding an instruction, said instruction including a hint field and being used to refill desired data to a first n-way, set associative, cache; and

a first multiplexer, coupled to said queue, for choosing a first destination indicator used to direct refilling of said first cache with said desired data, said first destination indicator being chosen from a first portion of said hint field and an alternative indicator under control of a second portion of said hint field, said first portion specifying a first way for desired data identified as a first data type and a second way for desired data identified as a second data type, said first portion being operable in subsequent refill operations to consistently specify first and second way destinations for subsequent first data type and second data type data, respectively.

10. The processor of claim 9 wherein said first portion of said hint field points to said first way of said first cache, wherein said first way contains no desired data identified as second data type.

11. The processor of claim 9 wherein said first portion of said hint field points to said second way of said first cache, wherein said second way contains no desired data identified as first data type.

12. The processor of claim 9 further comprising:

a second multiplexer, coupled to said queue, for choosing a second destination indicator used to direct reading of said desired data from a second cache.

13. The processor of claim 9 wherein said alternative indicator is a randomly generated bit.

17. The processor of claim 9 wherein said first data type and said second data type are streamed data and retained data, respectively.

18. The processor of claim 9 wherein said alternative indicator is an LRU bit.

21. In a processor with an n-way, set associative, cache, a method comprising:

issuing an instruction, wherein said instruction includes a hint field; and

specifying a refill destination for desired data within the cache using said hint field, said destination being a first way in said cache when said desired data is a first type of data and a second way in said cache when said desired data is a second type of data, wherein subsequent hint fields in subsequent instructions are operable to consistently specify such way destinations for subsequent first and second types of data.

22. A processor comprising:

an n-way, set associative, cache containing a cache line that is addressed using address information contained in an instruction, said instruction also containing a hint field; and

a multiplexer, coupled to said n-way cache, for choosing a destination indicator that is used to direct refilling of said cache line with desired data, said destination indicator being chosen from information contained in said hint field and an alternative indicator, said information specifying a first way for desired data identified as a first data type and a second way for desired data identified as a second data type, and wherein subsequent hint fields disposed in subsequent instructions contain subsequent information that is operable to consistently specify first and second way destinations for subsequent first data type and second data type data, respectively, in subsequent refill operations.

23. The processor of claim 22 wherein said alternative indicator specifies said first way and second way randomly.

24. A processor comprising:

a queue for holding an instruction, said instruction including a hint field; and

an n-way, set associative, cache coupled to said queue that is operable to receive desired data in accordance with said hint field, wherein said hint field specifies a first way for receiving desired data identified as a first data type and a second way for receiving desired data identified as a second data type, and subsequent instructions contain hint fields that are operable to consistently specify first and second way destinations for subsequent first data type and second data type data, respectively.