Digital signal processor with management of memory allocation between program and data memory

• US 6,240,497 B1
• Filed: 05/26/1998
• Issued: 05/29/2001
• Est. Priority Date: 05/27/1997
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Yagi, Minoru
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/084,803
• Time in Patent Office: 1,099 Days
• Field of Search: 710/127, 710/128, 710/170, 711/172, 711/171, 711/212
• US Class Current: 711/170
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a memory system, a plurality of memories having different bit widths from each other and each including at least one block and a plurality of buses are provided. At least one selector is connected between the block and at least two of the buses and selectively connects the block to one of the at least two buses.

Claims

1. A memory system comprising:

a first memory having a first bid width;

a second memory having a second bit width different from the first bit width;

the first memory being comprised of a first and a second memory block;

the second memory being comprised of at least a first memory block;

a first bus;

the first memory block in the first memory being connected to the first bus;

a second bus;

the first memory block in the second memory being connected to the second bus;

a first selector circuit; and

a circuit which generates a selection signal for the first selector circuit,

the first selector circuit being responsive to a first value of the selection signal to connect the second memory block in the first memory to the first bus, and responsive to a second value of the selection signal to associate the second memory block in the first memory with the second memory by connecting the second memory block in the first memory to the second bus.

2. A memory system as described in claim 1, in which:

the second memory is comprised of a first memory unit and a second memory unit, each memory unit being comprised of at least one memory block;

the second bus is comprised of a first bus unit connected to the first memory block in the first memory unit and a second bus unit connected to the first memory block in the second memory unit; and

the first selector circuit is operative in response to the second value of the selection signal to connect a first part of the second memory block in the first memory to the first bus unit, and to connect a second part of the second memory block in the first memory to the second data bus unit.

3. A memory system as described in claim 2, in which:

the first part of the second memory block in the first memory has a third bit width;

the second part of the second memory block in the first memory has a fourth bit width,

the third and fourth bit widths being respectively equal to the first and second bit widths.

4. A memory system as described in claim 3, in which the first through the fourth bit widths are all equal.

5. A memory system as described in claim 2, in which:

the first and second data memory units are each further comprised of;

a second memory block; and

further including

a second selector circuit;

a circuit for generating a second selection signal;

the second selector circuit being operative in response to a first value of the second selection signal to connect the second memory block in the first memory unit to the first bus unit, and operative in response to a second value of the second selection signal to connect the second memory block in the first memory unit to the first bus;

a third selector circuit,

a circuit for generating a third selection signal;

the third selector circuit being operative in response to a first value of the third selection signal to connect the second memory block in the second data memory unit to the second data bus unit, and operative in response to a second value of the third selection signal to connect the second memory block in the second data memory unit to the first bus.

6. A memory system according to claim 5, in which values of the second and third selection signals are set simultaneously in their respective first or second states.

7. A memory system as described in claim 1, in which:

the second memory is comprised of;

a first and a second memory unit, each including respective first and second memory blocks; and

further including

a second selector circuit;

a circuit for generating a second selection signal;

the second selector circuit being operative in response to a first value of the second selection signal to connect the second memory block in the first memory unit to the first bus unit and operative in response to a second value of the second selection signal to connect the second memory block in the first memory unit to the first bus;

a third selector circuit,

a circuit for generating a third selection signal;

the third selector circuit being operative in response to a first value of the third selection signal to connect the second memory block in the second data memory unit to the second data bus unit, and operative in response to a second value of the third selection signal to connect the second memory block in the second data memory unit to the first base.

8. A memory system according to claim 7, in which values of the second and third selection signals are set simultaneously in their respective first or second states.

9. A memory system comprising:

a data memory which stores data to be processed by a computer program;

an instruction memory, the instruction memory including;

a first memory block which is solely allocated for storage of program instructions for processing data stores in the first memory; and

a second memory block which may be selectively allocated for storage of program instructions or storage of data to be processed;

a data bus connected to the data memory;

an instruction bus connected to the first memory block in the instruction memory;

a first selector circuit,

the first selector circuit being operative in a first state to connect the second memory block in the instruction memory to the instruction bus, and operative in a second state to connect the second memory block in the instruction memory to the data bus; and

a control circuit which is operative to select the state of the first selector circuit,

whereby the second memory block in the instruction memory may be used for storing instructions or data as required.

10. A memory system as described in claim 9, in which:

the data memory is comprised of a first memory unit and a second memory unit;

the data bus is comprised of a first data bus unit connected to the first memory unit and a second data bus unit connected to the second memory unit; and

the first selector circuit is operative in the second state to connect a first part of the second memory block in the instruction memory to the first data bus unit, and to connect a second part of the second memory block in the instruction memory to the second data bus unit.

11. A memory system as described in claim 10, in which:

the first data memory unit and the first data bus unit have a first bit width;

the second data memory unit and the second data bus unit have a second bit width; and

the instruction memory and the instruction bus have a third bit width greater than the first and second bit widths.

12. A memory system as described in claim 11, in which the bit widths of the first and second parts of the second memory block in the instruction memory are respectively equal to the first and second bit widths.

13. A memory system as described in claim 12, in which:

the first and second bit widths are equal to one-half the third bit width.

14. A memory system as described in claim 10, in which:

the first and second data memory units are each comprised of;

a first memory block which is solely allocated to storage of data; and

a second memory block which may be selectively allocated for storage of data or storage of program instructions; and

further including

a second selector circuit;

the second selector circuit being operative in a first state to connect the second memory block in the first data memory unit to the first data bus unit, and operative in a second state to connect the second memory block in the first data memory unit to the instruction bus; and

a third selector circuit,

the third selector circuit being operative in a first state to connect the second memory block in the second data memory unit to the second data bus unit, and operative in a second state to connect the second memory block in the second data memory unit to the instruction bus.

15. A memory system according to claim 14, further including second and third control circuits which are operative to set the second and third selector circuits simultaneously in their respective first or second states.

16. A memory system for a data processing device comprising:

a first memory which performs a first function;

a second memory, the second memory including;

a first memory block which is solely allocated for performance of a second function; and

a second memory block which may selectively be allocated for performance of the first function or the second function;

a first bus connected to the first memory;

a second bus connected to the first memory block in the second memory;

a first selector circuit,

the first selector circuit being operative in a first state to connect the second memory block in the second memory to the second bus, and operative in a second state to connect the second memory block in the second memory to the first bus; and

a control circuit which is operative to set the first selector circuit in its first or second state,

whereby the second memory block in the second memory may be used for performing the first or the second function as required.

17. A memory system as described in claim 16, in which:

the first memory is comprised of a first memory unit and a second memory unit;

the first bus is comprised of a first bus unit connected to the first memory unit and a second bus unit connected to the second memory unit; and

the first selector circuit is operative in the second state to connect a first part of the second memory block in the second memory to the first bus unit, and a second part of the second memory block in the second memory to the second bus unit.

18. A memory system as described in claim 17, in which:

the first memory unit and the first bus unit have a first bit width;

the second memory unit and the second bus unit have a second bit width; and

the second memory and the instructions bus have a third bit width greater than the first and second bit widths.

19. A memory system as described in claim 18, in which the bit widths of the first and second parts of the second memory block in the second memory are respectively equal to the first and second bit widths.

20. A memory as described in claim 19, in which the first and second bit widths are equal to one-half the third bit width.

21. A memory system as described in claim 17, in which:

the first and second memory units are each comprised of;

a first memory block which is solely allocated to perform the first function; and

a second memory block which may be selectively allocated to perform the first or the second function; and

further including;

a second selector circuit,

the second selector circuit being operative in a first state to connect the second memory block in the first memory unit to the first bus unit, and operative in a second state to connect the second memory block in the first memory unit to the second bus; and

a third selector circuit,

the third selector circuit being operative in a first state to connect the second memory block in the second memory unit to the second bus unit, and operative in a second state to connect the second memory block in the second memory unit to the second bus.

22. A memory system according to claim 21, further including second and third control circuits which are operative to set the second and third selector circuits simultaneously in their respective first or second states.

23. A memory system as described in claim 21 in which:

the second function is storage of data to be processed by a computer program; and

the first function is storage of program instructions for processing the data stored in the second memory.

24. A memory system as described in claim 16, in which:

the first function is storage of data to be processed by a computer program; and

the second function is storage of program instructions for processing the data stored in the first memory.

25. A memory system as described in claim 16, in which:

the second function is storage of data to be processed by a computer program; and

the first function is storage of program instructions for processing the data stored in the second memory.

26. An integrated circuit digital signal processor comprising:

an internal data memory which stores data to be acted on by the digital signal processor;

an internal data bus connected to the internal data memory;

a internal instruction memory, the internal instruction memory including;

a first memory block which is allocated solely for storage of program instructions for processing data stored in the internal data memory; and

a second memory block which may be selectively allocated for storage of data or program instructions;

an internal instruction bus connected to the first memory block in the internal instruction memory;

a first selector circuit connected to the second memory block in the internal instruction memory,

the first selector circuit being operative in a first state to connect the second memory block in the internal instruction memory to the internal instruction bus and operative in a second state to connect the second memory block in the internal instruction memory to the internal data bus; and

a first control circuit which is operative to select the state of the first selector circuit.

27. A digital signal processor as described in claim 26, in which:

the internal data memory is comprised of a first memory unit and a second memory unit,

the internal data bus is comprised of a first data bus unit connected to the first memory unit and a second data bus unit connected to the second memory unit; and

the first selector circuit is operative in the second state to connect a first part of the second memory block in the internal instruction memory to the first data bus unit, and to connect a second part of the second memory block in the internal instruction memory to the second data bus unit.

28. A digital signal processor as described in claim 27, in which:

the first data memory unit and the first data bus unit have a first bit width;

the second data memory unit and the second data bus unit have a second bit width; and

the instruction memory and the instruction bus have a third bit width greater that the first and second bit widths.

29. A digital signal processor as described in claim 28, in which the bit widths of the first and second parts of the second memory block in the internal instruction memory are respectively equal to the first and second bit widths.

30. A digital signal processor as described in claim 29, in which:

the first and second bit widths are equal to one-half the third bit width.

31. A digital signal processor as described in claim 27, in which:

the first and second data memory units are each comprised of;

a first memory block which is solely allocated to storage of data; and

a second memory block which may be selectively allocated for storage of data or storage of program instructions; and

further comprising

a second selector circuit,

the second selector circuit being operative in a first state to connect the second memory block in the first data memory unit to the first data bus unit, and operative in a second state to connect the second memory block in the first data memory unit to the internal instruction bus; and

a third selector circuit,

the third selector circuit being operative in a first state to connect the second memory block in the second data memory unit to the second data bus unit, and operative in a second state to connect the second memory block in the second data memory unit to the internal instruction bus.

32. A digital signal processor as described in claim 31, further including second and third control circuits which are operative to set the second and third selector circuits simultaneously in their respective first or second states.

33. An integrated circuit digital signal processor comprising:

an internal data memory, which stores data to be acted upon by the digital signal processor,

an internal data bus connected to the internal data memory;

an internal instruction memory, the internal instruction memory including;

a first memory block which is allocated solely for storage of program instructions; and

a plurality of second memory blocks which may selectively be allocated for storage of data or program instructions;

a plurality of first selector circuits, each of the first selector circuits being associated with a respective one of the second memory blocks in the internal instruction memory, and operative in a first state to connect the second memory block to the internal program instruction bus and operative in a second state to connect the associated second memory block to the internal data bus; and

a first control circuit which is operative to select the states of each of the first selector circuits.

34. A digital signal processor as described in claim 33, in which:

the internal data memory is comprised of a first memory unit; and

a second memory unit,

the internal data bus is comprised of a first data bus unit connected to the first memory unit and a second data bus unit connected to the second memory unit; and

each of the first selector circuits is operative in the second state to connect a first part of the associated second memory block in the internal instruction memory to the first data bus unit, and to connect a second part of the associated second memory block in the instruction memory to the second data bus unit.

35. A digital signal processor as described in claim 34, in which:

the first data memory unit and the firs data bus unit have a first bit width;

the second data memory unit and the second data bus unit have a second bit width; and

the instruction memory and the instruction bus have a third bit width greater than the first and second bit widths.

36. A digital processor as described in claim 35, in which the bit width of the first and second parts of the second memory block in the internal instruction memory are respectively equal to the first and second bit widths.

37. A digital signal processor as described in claim 35, in which:

the first and second bit widths are equal to one-half the third bit width.

38. A digital signal processor as described in claim 34, in which the first and second data memory units are each comprised of:

a first memory block which is solely allocated to storage of data; and

a plurality of second memory blocks each of which may be selectively allocated for storage of data or storage of program instructions; and

further comprising;

a plurality of second selector circuits, each associated one of the second memory blocks in the first data memory unit,

each of the second selector circuits being operative in a first state to connect the associated second memory block in the first data memory unit to the first data bus unit, and operative in a second state to connect the second memory block in the first data memory unit to the instruction bus; and

a plurality of third selector circuits, each associated one of the second memory blocks in the second data memory unit,

each of the third selector circuits being operative in a first state to connect the associated second memory block in the second data memory unit to the second data bus unit, and operative in a second state to connect the associated second memory block in the second data memory unit to the instruction bus.

39. A digital signal processor as described in claim 38, further including second and third control circuits which are operative to set the second and third selector circuits simultaneously in their respective first or second states.