Motor vehicle speed monitoring system

• US 6,240,773 B1
• Filed: 03/15/1999
• Issued: 06/05/2001
• Est. Priority Date: 03/15/1999
• Status: Expired due to Fees

• Current Assignee: John Rita, Miki Rita
• Original Assignee: John Rita, Miki Rita
• Inventors: Rita, John, Rita, Miki
• Primary Examiner(s): MCCALL, ERIC SCOTT
• Application Number:
  US09/270,251
• Time in Patent Office: 813 Days
• Field of Search: 731/16, 731/172, 731/173, 731/181, 734/88, 734/89, 116/62.1, 116/62.2, 116/62.3, 116/62.4, 340/441, 340/466
• US Class Current: 73/114.01
• CPC Class Codes: G01D 9/005 Solid-state data loggers
• CPC Class Codes: G07C 5/085 using electronic data carriers

Abstract

A motor vehicle speed monitoring system is disclosed as a device to acquire and record the top speed obtained by a motor vehicle during each operating session. Such monitoring allows for the security that one'"'"'s children, employees, valets, mechanics, or others entrusted with the care of a vehicle have not operated it above acceptable speed limits. The system digitally records the top speed of the vehicle every time it is started and keeps a log of the speed and the time and dates at which it occurred. The owner or authorized user may review the internal log by entering a password key into a keypad.

Claims

1. A motor vehicle speed monitoring system for use with a motor vehicle having an engine compartment, said motor vehicle speed monitoring system comprising:

an electronics enclosure, said enclosure located within an engine compartment;

an operating panel, said operating panel positioned on a face of said electronics enclosure, said operating panel comprising an output display and an input keypad, said output display for providing output feedback and said input keypad for providing input by a user into the motor vehicle speed monitoring system;

control circuitry, allowing the recording of said motor vehicle'"'"'s speed in an unattended manner, including recording the top speed of the vehicle each time the vehicle is driven and keeping a log of the speed, the time, and the date at which the top speed of the vehicle occurred, said control circuitry making an actual determination of speed through a speed detection device connected to a main processor unit by a speed acquisition cable, wherein said main processor unit is located within said electronics enclosure, and said speed detection device is mechanically connected to a vehicle speedometer for the determination of speed, wherein said control circuitry comprises;

a first functional block;

a second functional block;

a third functional block;

a first operational block, whereupon a negative response generates a loop configuration within the first operation block and a positive response directs the recording of the measured speed via a second functional block;

a fourth functional block wherein a second speed measurement is obtained, speed as obtained in the second functional block and speed as obtained in the fourth functional block are compared in a second operational block, a negative response directing process back to third functional block and a positive response directing a storing of the data acquired in the second operational block as well as the time and date said speed were acquired in a fifth functional block and then directing process back to the third functional block with a negative response until the motor vehicle is turned off, wherein a final highest speed value as determined by the second operational block is a stored value;

a sixth functional block for accessing speed measurement as obtained in the second functional block and storing said speed measurement in a maximum speed memory stack along with a date and time stamp, output of sixth functional block then communicated onto a third operational block where a determination is made if speed stored in the sixth functional block is above a preset default value;

a negative response to the third operational block thereby dictating an obtaining of another speed measurement by a seventh functional block and a corresponding return of logic control to the third operational block; and

, a positive response to the third operational block dictating a storing of speed along with a date and time stamp in the maximum speed memory stack by an eighth functional block;

a fourth operational block wherein a determination is made if speed has dropped below the preset default value as explained in the third operational block, a negative response providing for the continuation of the loop until speed has dropped below the preset default value and a positive response dictating that the logic control returns to the third operational block;

and wherein entire communication between the sixth functional block and the fourth operational block provides for the recording of each speed incident that exceeds the preset default value.