Method of manufacturing integrated circuits

• US 6,242,270 B1
• Filed: 02/09/1999
• Issued: 06/05/2001
• Est. Priority Date: 02/10/1998
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Van Wezep, Dries A., Nagaswami, Venkat R., Van Gessel, Johannes G.
• Primary Examiner(s): Tsai, Jey
• Assistant Examiner(s): LUK, OLIVIA T
• Application Number:
  US09/247,783
• Time in Patent Office: 847 Days
• Field of Search: 438/14, 382/145, 356/237.4, 364/468
• US Class Current: 438/14
• CPC Class Codes: H01L 21/67288 Monitoring of warpage, curvature, damage, defects or the like
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Visible defects are detected on a process semiconductor wafer. Defects are classified according to appearance and an association is kept between classes and apparatuses. When the density of defects in a given class exceeds a control limit the associated apparatus is switched off-line. In an embodiment, the same wafer is inspected repeatedly, each time after a different processing steps and information about the location of detected defects is kept. Defects which occur at a location where defects have already been detected in a previous inspection after an earlier processing step are eliminated from the density which is compared to the control limit.

Claims

1. A method of manufacturing integrated circuits, the method comprising the steps of:

processing a wafer with an apparatus;

counting a number of visible defects on the wafer after processing with said apparatus;

automatically identifying the apparatus as malperforming if the number exceeds a control limit;

characterized in that the method comprises;

defining classes of defect types in terms of visible appearance and defining for each class a respective control limit;

maintaining an association associating classes with apparatus types used in processing steps;

performing the processing steps on a wafer;

determining respective numbers of defects of different classes on the wafer after performing said processing steps;

comparing the respective number for each class to the control limit for that class,

if the respective number of defects of a particular class exceeds the control limit for that particular class, automatically using the association to find the particular processing step and particular apparatus type associated with that particular class, and bringing a particular apparatus off-line that is of said particular apparatus type and has been used in that particular processing step.

2. A method according to claim 1, wherein said determining step is performed at a first stage during processing of the wafer, the method comprising

detecting locations of further defects on the wafer at a second stage, at least one of said processing steps following the second stage and preceding the first stage,

said determining of the respective numbers comprising counting visible defects at the first stage, only such visible defects being counted which do not lie at a location on the wafer where further defects have been detected at the second stage.

3. A method according to claim 1, wherein said determining step is performed at a first stage during processing of the wafer, the method comprising

counting a count of visible defects at the first stage,

further determining a further number of defects on the wafer at a second stage, said processing steps following the second stage and preceding the first stage,

the number of defects being determined by subtracting from the count of defects an estimated prior number of defects derived from said further number.

4. A method according to claim 1, wherein the defects of at least one class are clustered into spatially localized clusters of defects, said respective number of defects in said at least one class being at most counts of clusters, rather than counts of individual defects.

5. A method according to claim 1, wherein said counting is performed only for a sub-area or sub-areas of the wafer.

6. A method according to claim 1, comprising detecting defects by detecting deviations between patterns on the wafer to reference patterns, the detected defects being subsequently classified according to visual appearance.

7. A method according to claim 1, wherein at least said defining, maintaining, counting, comparing and witching off-line steps are performed automatically using a factory control computer system.