Method for forming self-aligned contact

• US 6,242,332 B1
• Filed: 08/27/1999
• Issued: 06/05/2001
• Est. Priority Date: 08/29/1998
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Chang-Hyun, Kim, Ki-Nam, Chung, Tae-Young
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/384,281
• Time in Patent Office: 648 Days
• Field of Search: 438/238, 438/239, 438/241, 438/297, 438/303, 438/587, 438/588, 438/591, 438/622, 438/629
• US Class Current: 438/587
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

The size of a pad in the present invention is reduced, thereby preventing a polymer etch-stop, suppressing a short between a gate and a gate conductive layer exposed by the damage of an oxide layer covering the gate conductive layer, and extending a top surface area of a pad beyond the technical limitation of a photo equipment. As a result, it is possible to greatly secure the alignment of a buried contact electrically connected to the pad.

Claims

1. A method for forming a self-aligned contact of a semiconductor device, comprising:

forming a conductive layer over a semiconductor substrate;

forming a first multiple insulating layer over the conductive layer, the first multiple insulating layer including a first insulating layer and a second insulating layer that has an etching selectivity with respect to the first insulating layer;

forming a second multiple insulating layer over the first multiple insulating layer, the second multiple insulating layer including a third insulating layer and a fourth insulating layer, the third insulating layer having an etching selectivity with respect to both the second and fourth insulating layers;

forming a plurality of gate electrodes by etching the conductive layer, the first multiple insulating layer, and the second multiple insulating layer using a gate electrode formation mask;

forming a spacer on gate sidewalls of the gate electrode, the spacer having an etch selectivity with respect to the fourth insulating layer;

forming an interlayer insulating layer over the semiconductor substrate to fill spaces between the gate electrodes, the interlayer insulating layer having a etching selectivity with respect to the third insulating layer;

etching the interlayer insulating layer until a top surface of the semiconductor substrate between the gate electrodes is exposed, to form an opening;

forming a conductive layer over the interlayer insulating layer and in the opening; and

planarizing the conductive layer to form a pad.

2. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 1, further comprising

forming a fifth insulating layer over the semiconductor substrate and the gate electrodes subsequent to the forming of the spacer, using a pad formation mask; and

etching the interlayer insulating layer until the fifth insulating layer over the semiconductor substrate and adjacent to the gate electrode is exposed.

3. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 2, wherein etching the interlayer insulating layer until a top surface of the semiconductor substrate between the gate electrodes is exposed comprises:

etching the fourth and fifth insulating layers and a portion of the sidewall spacer; and

etching a portion of the sidewall spacer exposing a lateral surface of the third insulating layer.

4. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 3, wherein the planarizing of the conductive layer is performed down to a top surface of the third insulating layer.

5. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 2, wherein etching the interlayer insulating layer until a top surface of the semiconductor substrate between the gate electrodes is exposed comprises:

etching the fourth and fifth insulating layers;

etching an upper portion of the spacer to expose sidewalls of the first and second multiple insulating layers; and

isotropically etching sidewall portions of the exposed second insulating layer to cause an undercut portion between the first and third insulating layers.

6. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 5, wherein the planarizing of the conductive layer is performed until a top surface of the second insulating layer is exposed.

7. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 5, wherein the isotropic etching of the second insulating layer is performed until a minimum thickness of the second insulating layer is left to insulate the pad from an adjacent pad.

8. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 7, wherein the minimum thickness of the second insulating layer is about 400 Å

.

9. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 5, wherein the spacer comprises SiN, and has a thickness of about 300 to 1,000 Å

from a sidewall of the gate electrode.

10. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 1, wherein the first and third insulating layers comprise SiN, and the second and fourth insulating layers comprise an oxide.

11. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 1, wherein the first insulating layer has a thickness of about 500 to 1,000 Å

, the second insulating layer has a thickness of about 500 to 1,000 Å

, the third insulating layer has a thickness of about 500 to 700 Å

, and the fourth insulating layer has a thickness of about 300 to 500 Å

.

12. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 1, wherein the pad fortmation mask is T-type.

13. A method for forming a self-aligned contact of a semiconductor device, as recited in claim 1, wherein the spacer comprises SiN and has a thickness of about 300 to 1,000 Å

from a sidewall of the gate electrode.

14. A method for forming a self-aligned contact of a semiconductor device, comprising:

forming a conductive layer over a semiconductor substrate;

forming a first insulating layer over the conductive layer;

forming a second insulating layer over the first insulating layer;

forming a third insulating layer over the second insulating layer;

forming a fourth insulating layer over the third insulating layer;

forming a gate electrode by etching the conductive layer and the first through fourth insulating layers;

forming a spacer on sidewalls of the gate electrode;

forming a fifth insulating layer over the semiconductor substrate, the gate electrode, and the spacer;

forming an interlayer insulating film over the fifth insulating layer to fill a space between the gate electrode and an adjacent gate electrode;

etching the interlayer insulating layer and the fifth insulating layer between the gate electrode and the adjacent gate electrode to form an opening exposing the semiconductor substrate,

wherein an upper portion of the spacer is etched to expose sidewalls of the first and second multiple insulating layer, and sidewall portions of the exposed second insulating layers are isotropically etched to cause an undercut portion between the first and third insulating layers;

forming a conductive layer over the interlayer insulating film and in the opening; and

forming a pad by planarizing the conductive layer down to remove any portion outside of the opening.