Method of forming copper/copper alloy interconnection with reduced electromigration

• US 6,242,349 B1
• Filed: 12/09/1998
• Issued: 06/05/2001
• Est. Priority Date: 12/09/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Nogami, Takeshi, Lopatin, Sergey, Joo, Young-Chang
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/207,680
• Time in Patent Office: 909 Days
• Field of Search: 438/687, 438/628, 438/643, 438/629, 438/627, 438/622, 438/637, 438/653, 438/659, 438/674, 438/678, 205/184
• US Class Current: 438/687
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer

Abstract

The electromigration of a Cu or Cu alloy interconnection member is reduced by annealing the seed layer before electroplating or electroless plating the Cu or Cu alloy interconnection member on the seed layer. Embodiments include depositing a Cu or Cu alloy seed layer, annealing at about 100° C. to about 400° C. to increase the grain size of the seed layer and impart a (111)-dominant crystallographic option before plating the Cu or Cu alloy interconnect member thereon the seed layer

Claims

1. A method comprising:

depositing a seed layer having an as-deposited first grain size;

annealing the seed layer to increase its grain size to a second grain size greater than the first grain size; and

electroplating or electroless plating copper (Cu) or a Cu alloy on the annealed seed layer.

2. The method according to claim 1, comprising manufacturing a semiconductor device.

3. The method according to claim 2, comprising annealing such that the seed layer exhibits a (111)-dominant crystallographic orientation.

4. The method according to claim 2, comprising:

depositing a Cu or Cu alloy seed layer by sputtering or chemical vapor deposition at a thickness of about 50 Å

to about 3000 Å

; and

annealing at a temperature of about 100°

C. to about 400°

C.

5. The method according to claim 4 comprising annealing for about 30 seconds to about 30 minutes in a vacuum or in an atmosphere comprising argon, nitrogen or hydrogen.

6. The method according to claim 4, wherein the seed layer comprises an alloy of Cu and about 0.1 to about 5 at. % of tin, magnesium, palladium or zirconium.

7. The method according to claim 2, wherein:

the first grain size is about 0.05 μ

m to about 0.5 μ

m; and

the second grain size is about 0.5 μ

m to about 3 μ

m.

8. The method according to claim 2, further comprising:

forming a dielectric layer overlying a substrate;

forming an opening in the dielectric layer,

depositing a Cu or Cu alloy seed layer in the opening;

annealing the seed layer;

electroplating or electroless plating a Cu or Cu alloy layer on the seed layer in the opening and over the dielectric layer; and

removing any portion of the Cu or Cu alloy layer beyond the opening.

9. The method according to claim 8, comprising:

depositing a barrier layer in the opening; and

depositing the seed layer on the barrier layer.

10. The method according to claim 8, wherein:

the opening is a trench; and

the plated Cu or Cu alloy layer forms an interconnecting line.

11. The method according to claim 10, wherein:

the opening further comprises a via or contact hole in communication with the trench; and

the plated Cu or Cu alloy layer comprises a first portion filling the trench forming an interconnection line and a second portion filling the hole forming a via or contact in electrical communication with the interconnection line.

12. The method according to claim 8, wherein:

the opening comprises a via or contact hole; and

the plated Cu or Cu alloy layer forms a via or contact.

13. The method according to claim 2, wherein the plated Cu or Cu alloy exhibits a grain size of about 0.5 μ

m to about 3 μ

m.

14. The product produced by the method according to claim 2.

15. The method according to claim 1, comprising depositing a Cu or Cu alloy seed layer.

16. The method according to claim 1, comprising electroless plating the Cu or Cu alloy on the annealed seed layer.