Low triggering voltage SOI silicon-control-rectifier (SCR) structure

• US 6,242,763 B1
• Filed: 09/14/1999
• Issued: 06/05/2001
• Est. Priority Date: 09/14/1999
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wang, Mu-Chun, Chou, Jih-Wen, Tang, Tien-Hao, Chen, Shiao-Shien
• Primary Examiner(s): Flynn, Nathan
• Assistant Examiner(s): MacDonald, Brian D.
• Application Number:
  US09/396,163
• Time in Patent Office: 630 Days
• Field of Search: 257/107, 257/119, 257/162, 257/146, 257/173
• US Class Current: 257/107
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes

Abstract

A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure is disclosed. In one embodiment, the protection structure includes: A semiconductor substrate; a thin film layer separated from a bulk silicon substrate by an insulator inside the semiconductor substrate; a first isolation region formed in the thin film layer; a second isolation region formed in the thin film layer; a first region having a first conductivity type formed in between the first and second isolation region; a second region formed in between the first region and the second isolation region, the second region being of a second conductivity type; a third region formed in between the first isolation region and the first region, the third region being of the first conductivity type; a fourth region formed in between the second isolation region and the second region, the fourth region being of the first conductivity type; a fifth region having an exposed upper surface formed in the first region, the fifth region being of the second conductivity type; a sixth region having an exposed surface formed in the second region, the sixth region being of the second conductivity type; and a seventh region having an exposed upper surface formed in the second region and overlapping the first region, moreover, the seventh region being between the fifth and sixth region and the seventh region being of the first conductivity type. Another embodiment of the present invention is very similar to the previous one, which is also extracted in the present specification.

Claims

1. A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure, said protection structure comprises:

a semiconductor substrate;

a thin film layer separated from a bulk silicon substrate by an insulator inside said semiconductor substrate;

a first isolation region formed in said thin film layer;

a second isolation region formed in said thin film layer;

a first region having a first conductivity type formed in between said first and second isolation region but not adjoining to any of them;

second region formed in between said first region and said second isolation region but only adjoining to said first region, said second region being of a second conductivity type which is different to said first conductivity type;

a third region formed in between said first isolation region and said first region, said third region being of said first conductivity type;

a fourth region formed in between said second isolation region and said second region, said fourth region being of said first conductivity type;

a fifth region having an exposed upper surface formed in said first region, said fifth region being of said second conductivity type;

a sixth region having an exposed surface formed in said second region, said sixth region being of said second conductivity type;

a seventh region having an exposed upper surface formed in said second region and overlapping said first region, moreover, said seventh region is in between said fifth and sixth region, said seventh region being of said first conductivity type;

a first contact on said structure coupled to said third region and said fifth region; and

a second contact on said structure coupled to said fourth region and said sixth region.

2. The protection structure in accordance with claim 1, wherein said first conductivity type is p-type.

3. The protection structure in accordance with claim 1, wherein said second conductivity type is n-type.

4. The protection structure in accordance with claim 2, wherein said third region is p-type of a higher doping level than said first region.

5. The protection structure in accordance with claim 2, wherein said fourth region is p-type of a higher doping level than said first region.

6. The protection structure in accordance with claim 3, wherein said fifth region is n-type of a higher doping level than said second region.

7. The protection structure in accordance with claim 3, wherein said sixth region is n-type of a higher doping level than said second region.

8. The protection structure in accordance with claim 2, wherein said seventh region is p-type of a higher doping level than said first region, and having a doping concentration in a range of about 1×

10¹⁸ to about 1×

10¹⁹ cm<sup>−

3</sup>.

9. The protection structure in accordance with claim 1, wherein said first and second contact form the cathode and anode of a silicon-control-rectifier device respectively.

10. The protection structure in accordance with claim 1, wherein said sixth and seventh region form the n⁺-p⁺ junction of a zener diode.

11. The protection structure in accordance with claim 1, wherein said insulator comprises oxide.

12. The protection structure in accordance with claim 1, wherein said thin film layer has a thickness of more than about 1000 angstroms.

13. The protection structure in accordance with claim 1, wherein said first and second isolation region comprise silicon dioxide.

14. A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure, said protection structure comprises:

a semiconductor substrate;

a thin film layer separated from a bulk silicon substrate by an insulator inside said semiconductor substrate;

a first isolation region formed in said thin film layer;

a second isolation region formed in said thin film layer;

a first region having a first conductivity type formed in between said first and second isolation region but not adjoining to any of them;

a second region formed in between said first region and said second isolation region but only adjoining to said first region, said second region being of a second conductivity type which is different to said first conductivity type;

a third region formed in between said first isolation region and said first region, said third region being of said second conductivity type;

a fourth region formed in between said second isolation region and said second region, said fourth region being of said second conductivity type;

a fifth region having an exposed upper surface formed in said first region, said fifth region being of said first conductivity type;

a sixth region having an exposed surface formed in said second region, said sixth region being of said first conductivity type;

a seventh region having an exposed upper surface formed in said first region and overlapping said second region, moreover, said seventh region is in between said fifth and sixth region, said seventh region being of said second conductivity type;

a first contact on said structure coupled to said third region and said fifth region; and

a second contact on said structure coupled to said fourth region and said sixth region.

15. The protection structure in accordance with claim 14, wherein said first conductivity type is p-type.

16. The protection structure in accordance with claim 14, wherein said second conductivity type is n-type.

17. The protection structure in accordance with claim 16, wherein said third region is n-type of a higher doping level than said second region.

18. The protection structure in accordance with claim 16, wherein said fourth region is n-type of a higher doping level than said second region.

19. The protection structure in accordance with claim 15, wherein said fifth region is p-type of a higher doping level than said first region.

20. The protection structure in accordance with claim 15, wherein said sixth region is p-type of a higher doping level than said first region.

21. The protection structure in accordance with claim 16, wherein said seventh region is n-type of a higher doping level than said second region, and having a doping concentration in a range of about 1×

10¹⁸ to about 1×

10¹⁹ cm<sup>−

3</sup>.

22. The protection structure in accordance with claim 14, wherein said first and second contact form the cathode and anode of a silicon-control-rectifier device respectively.

23. The protection structure in accordance with claim 14, wherein said fifth and seventh region form the p⁺-n⁺ junction of a zener diode.

24. The protection structure in accordance with claim 14, wherein said insulator comprises oxide.

25. The protection structure in accordance with claim 14, wherein said thin film layer has a thickness of more than about 1000 angstroms.

26. The protection structure in accordance with claim 14, wherein said first and second isolation region comprise silicon dioxide.