Circuits and methods using vertical complementary transistors

• US 6,242,775 B1
• Filed: 02/24/1998
• Issued: 06/05/2001
• Est. Priority Date: 02/24/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P.
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/028,805
• Time in Patent Office: 1,197 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/333, 257/350, 257/351, 257/374
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A method and structure for an improved, vertically configured inverter array is provided. The inverter includes a buried gate contact coupling the body regions of a complementary pair of transistors. An electrical contact couples the second source/drain regions of the complementary pair of transistors. The transistors are formed in vertical pillars of single crystalline semiconductor material.

Claims

1. An inverter, comprising:

a first vertically configured transistor formed within a first vertically configured structure extending outwardly from a semiconductor substrate;

a second vertically configured transistor formed within a second vertically configured structure extending outwardly from a semiconductor substrate;

an electrical contact between source/drain regions of the first and second vertically configured transistors to provide an output for the inverter; and

a single gate contact located in an isolation trench below a top surface of the first and the second vertically configured transistors, the gate contact interconnecting and shared between the vertically configured transistors wherein the gate contact comprises an input to the inverter.

2. The inverter of claim 1, wherein:

the first vertically configured transistor comprises a first transistor type having a number of sides, the first transistor having a body region and first and second source/drain regions;

the first transistor further having a gate that is associated with a side of the first transistor; and

the second vertically configured transistor comprises a second transistor type having a number of sides, the second transistor having a body region and first and second source/drain regions, the second transistor further having a gate that is associated with a side of the second transistor.

3. The inverter of claim 2, wherein the gate contact interconnects the gates of the first and second transistors.

4. The inverter of claim 2, wherein the electrical contact between first and second transistors is a tungsten shunt that interconnects an outer source/drain region of the first and second transistors.

5. The inverter of claim 2, wherein the body region and first and second source/drain regions of the second transistor are oppositely doped from the corresponding body region and first and second source/drain regions of the first transistor.

6. An inverter on a semiconductor substrate, comprising:

a first transistor formed in a first pillar of single crystalline semiconductor material that extends outwardly from the substrate, the pillar having a number of sides, the first transistor having a body region and first and second source/drain regions that are vertically aligned, the first transistor further having a gate that is associated with a side of the first transistor;

a second transistor formed in a second pillar of single crystalline semiconductor material that extends outwardly from the substrate having a number of sides, the second transistor having a body region and first and second source/drain regions formed within the second pillar, the second transistor further having a gate that is associated with a side of the second transistor, wherein the transistors comprise a complementary pair;

a gate contact buried below an active top surface of the first and the second transistors that is in communication with the body regions of both first and second transistors; and

a metal shunt forming an electrical contact between the first and second transistors.

7. The inverter of claim 6, wherein the first source/drain region of first transistor comprises a p+ silicon material.

8. The inverter of claim 6, wherein the first source/drain region of first transistor comprises n+ silicon material.

9. An inverter array, comprising;

multiple complementary pairs of transistors extending outwardly from a semiconductor substrate and having upper surfaces, each transistor in a pair having a vertically stacked body region and first and second source/drain regions, each transistor further having a gate;

an electrical contact between the second source/drain regions of the transistors in each complementary pair;

a plurality of isolation trenches extending parallel to and separating the multiple complementary pairs of transistors and between each transistor; and

a gate contact for each complementary pair of transistors, wherein the gate contact is buried below an active top surface of each complementary pair of transistors, wherein the gate contact is shared between the complementary pair of transistors and wherein the gate contact communicates with the body region of each transistor in the complementary pair.

10. The inverter array of claim 9, wherein the electrical contact couples the second source/drain regions of the transistors in the complementary pair.

11. The inverter array of claim 10, wherein the electrical contact is a tungsten shunt.

12. The inverter array of claim 11, wherein the electrical contact further includes an output to other ones of the multiple complementary pairs of transistors.

13. The inverter array of claim 12, wherein the gate contact further includes an electrical input adapted to receive electrical input from an external sources as well as other ones of the multiple complementary pairs of transistors.

14. The inverter array of claim 13, wherein the gate contact is located below the upper surface of the multiple complementary pairs of transistors.

15. An inverter array on a semiconductor substrate, comprising:

multiple complementary pairs of transistors extending outwardly from the substrate having an upper surface, and each transistor in the pair having a vertically stacked body region between first and second source/drain regions;

a gate contact for each complementary pair of transistors, the gate contact coupling to the body region of each transistor in the complementary pair, and wherein the gate contact is buried below the upper surface of the multiple complementary pairs of transistors;

an electrical input coupling to the gate contact of each complementary pair;

an electrical contact between the complementary transistors in each pair of transistors; and

an electrical output coupling to each electrical contact.

16. The inverter array of claim 15, wherein the gate contact couples to other ones of the multiple complementary pairs of transistors.

17. The inverter array of claim 15, wherein the electrical output couples to other ones of the multiple complementary pairs of transistors.

18. An integrated logic circuit, comprising:

multiple complementary pairs of transistors extending outwardly from the substrate having an upper surface, and further each transistor includes a vertically stacked body region between first and second source/drain regions;

a gate contact associated with each of the multiple complementary pairs, wherein the gate contact is shared between the complementary transistors, the gate contact coupling to the body region of each transistor in the pair, and wherein the gate contact is below the upper surface of the multiple complementary pairs of transistors, the gate contact providing an input such that each complementary pair of transistors forms an inverter;

an electrical contact between each complementary pair of transistors to provide an output such that each complementary pair of transistors forms an inverter; and

a metallization layer that selectively interconnects the inputs and outputs of the inverters to form a logic circuit that accepts inputs and produces one or more logical outputs.

19. An input/output device, comprising:

a functional circuit having a plurality of components;

a logic device coupled to the functional circuit, the logic device having at least one inverter, the inverter further comprising;

a complementary pair of transistors extending outwardly from a semiconducting substrate, each complementary pair having an upper surface, each transistor in the complementary pair having a vertically stacked body region between first and second source/drain regions, each transistor having a gate;

a gate contact coupling between the body region in the complementary pair of transistors in each pair, wherein the gate contact is buried below the upper surface of the multiple complementary pairs of transistors, the gate contact having an input for each inverter;

an electrical contact between the second source/drain regions in the complementary pair of transistors in each pair, the electrical contact having an output for the inverter; and

a metallization layer that selectively interconnects the inputs and outputs of the selected inverters in the array to implement the logical function form the functional circuit.