Cooling method for silicon on insulator devices

• US 6,242,778 B1
• Filed: 09/22/1998
• Issued: 06/05/2001
• Est. Priority Date: 09/22/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pierson, Bernadette Ann, Marmillion, Patricia McGuinness, Schmidt, Dennis Arthur, Palagonia, Anthony Michael
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Berezny, Neal
• Application Number:
  US09/158,813
• Time in Patent Office: 987 Days
• Field of Search: 257/720, 257/712, 257/713, 257/714, 257/347
• US Class Current: 257/347
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a silicon on insulator technology, cooling channels in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer, where the junction regions are separated from the substrate by an insulating layer. In a second embodiment, thermal conductors in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer where the junction regions are separated from the substrate by an insulating layer. Optionally, either the cooling channels or the thermal conductors may be enlarged such that a plurality of devices may be cooled by a single cooling channel or thermal conductor.

Claims

1. A structure for cooling individual semiconductor devices or groups of semiconductor devices fabricated in silicon on insulator technology, comprising:

a silicon substrate;

an insulating layer disposed over said substrate;

a semiconductor layer disposed over said insulating layer; and

at least one semiconductor device or group of semiconductor devices formed in said semiconductor layer and in said insulating layer; and

wherein said substrate has at least one channel formed therein, wherein the channel has an upper surface in contact with said insulating layer and at least a portion of the channel is located beneath said semiconductor device or group of semiconductor devices.

2. The electronic device of claim 1, wherein said substrate comprises silicon and said insulating layer comprises silicon oxide.

3. The electronic device of claim 2, further comprising a protective layer and wherein the channel has bottom and side surfaces which are coated with said protective layer.

4. The electronic device of claim 3, wherein said protective layer comprises silicon oxide.

5. The electronic device of claim 1, further comprising means for delivering a cooling fluid to the channel.

6. The electronic device of claim 1, wherein the channel includes a thermal conductor.

7. The electronic device of claim 6, wherein said thermal conductor comprises aluminum, copper or a refractory metal.

8. The electronic device of claim 1, wherein said refractory metal is tungsten.

9. The electronic device of claim 7, further comprising a thermal collector in contact with said thermal conductor and a heatsink in contact with said thermal collector.

10. The electronic device of claim 1, wherein said substrate includes a separate channel for each said semiconductor device.

11. The electronic device of claim 1, wherein said substrate includes a channel which is located beneath more than one semiconductor device.