Stacked bottom lead package in semiconductor devices

• US 6,242,798 B1
• Filed: 02/29/2000
• Issued: 06/05/2001
• Est. Priority Date: 11/22/1996
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Cha, Gi-Bon, Lee, Byeong-Duck
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/515,626
• Time in Patent Office: 462 Days
• Field of Search: 257/686, 257/685, 257/673, 257/690, 257/692, 257/693, 257/696, 257/698, 257/723, 257/730, 257/777, 257/684, 257/796, 257/712
• US Class Current: 257/673
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stacked bottom lead package for use in semiconductor devices includes leads that are bent along with the circumference of the body which has been premolded, wherein a chip is included inside the premolded body. The package configuration prevents solder fatigue of the lead due to heat carried via the extended lead and emitted out of the chip and decreases the area required for stacking semiconductor packages.

Claims

1. A semiconductor package comprising:

a chip having a plurality of pads;

a body having a first face opposite to a second face and enveloping said chip; and

a plurality of leads, each having first and second ends, wherein said first ends of said leads are connected to said pads, said leads being shaped so that said second ends of said leads contact said second face, said second ends of said leads being shaped substantially into an “

I”

shape.

2. The semiconductor package according to claim 1, wherein said material is an insulating adhesive.

3. The semiconductor package according to claim 1, wherein said leads are connected electrically with a plurality of said pads via wires.

4. The semiconductor package according to claim 1, wherein said body comprises a recess comprising a premolded part, and a filling part filling said recess.

11. The semiconductor package according to claim 1, further comprising a material attaching said lead to said chip.

5. A structure of semiconductor packages comprising:

first and second package bodies, each having a first face disposed opposite to a second face;

first and second chips each having a plurality of pads and encompassed respectively by said first and second package bodies; and

a plurality of leads, each having first and second ends, the first end being connected to one of said chip pads, wherein said leads of at least one of said first and second package bodies are shaped so that said second ends of said leads contact said second face of said respective package body and said second ends of said each lead of said first package body is shaped substantially into an “

I”

shape.

6. The semiconductor packages according to claim 5, wherein a plurality of said second package bodies connected electrically to one another are stacked on said first package bodies.

7. The semiconductor packages according to claim 5, wherein said second package body is stacked onto said front face of said body of said first package body.

8. The semiconductor packages according to claim 7, further comprising a plurality of second package bodies, wherein said second package bodies are stacked onto said second face of said first package body.

13. The semiconductor package according to claim 5, further comprising a material attaching said leads to said chip in each said body.

9. A semiconductor package comprising:

a chip having a plurality of pads;

a body having a first face opposite to a second face and enveloping said chip; and

a plurality of leads, each having first and second ends, wherein said first ends of said leads are connected to said pads, said leads being shaped so that said second ends of said leads contact said second face, said second ends of said leads being shaped substantially into a gulling shape.

12. The semiconductor package according to claim 9, further comprising a material attaching said lead to said chip.

10. A structure of semiconductor packages comprising:

first and second package bodies, each having a first face disposed opposite to a second face;

first and second chips each having a plurality of pads and encompassed respectively by said first and second package bodies; and

a plurality of leads, each having first and second ends, the first end being connected to one of said chip pads, wherein said leads of at least one of said first and second package bodies are shaped so that said second ends of said leads contact said second face of said respective package body and said second end of said each lead of said first package body is shaped substantially into a gulling shape.

14. The semiconductor package according to claim 10, further comprising a material attaching said leads to said chip in each said body.