Moisture enhanced ball grid array package

• US 6,242,802 B1
• Filed: 07/17/1995
• Issued: 06/05/2001
• Est. Priority Date: 07/17/1995
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gold, Glenn E., Miles, Barry M., Mullen, William B. III
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/502,993
• Time in Patent Office: 2,150 Days
• Field of Search: 257/667, 257/676, 257/738, 257/737, 257/778, 361/760, 361/807
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An integrated circuit package (10) comprises a semiconductor die (14), and a substrate (16) for receiving the semiconductor die. The substrate has an aperture(s) (18) below the semiconductor die for providing moisture relief during temperature excursions. The semiconductor die is wirebonded to the substrate. An encapsulant (12) seals the top surface of the semiconductor die and serves to bond the semiconductor die to the substrate. The encapsulant also covers portions of the top side of the substrate.

Claims

1. A leadless chip carrier package that does not have a die attach adhesive, comprising:

a printed circuit substrate having a die mounting area on a first side and having one or more vent openings located in the die mounting area, the vent openings extending through the substrate from the first side to a second opposing side, and the second side having a plurality of surface mount solder pads;

a semiconductor die disposed in the die mounting area and covering the vent openings, the semiconductor die electrically connected to the printed circuit substrate by at least one wirebond, and the semiconductor die lying directly on the substrate with no die attach adhesive between the die and the substrate; and

a plastic resin encapsulating the semiconductor die and providing a compressive force to secure the semiconductor die in direct and intimate contact with the printed circuit substrate die mounting area, the plastic resin further encapsulating the at least one wirebond and covering portions of the printed circuit substrate first side.

2. The leadless chip carrier package of claim 1, wherein a perimeter portion of the substrate first side is not covered with the plastic resin.

3. The leadless chip carrier package of claim 1, wherein the plastic resin comprises a glob top encapsulant or a transfer molded encapsulant.

4. The leadless chip carrier package of claim 3, wherein the plurality of surface mount solder pads comprises a pad grid array.

5. The leadless chip carrier package of claim 3, wherein the plurality of surface mount solder pads comprises a peripheral array.