Multiplexed synchronization circuits for switching frequency synthesized signals

• US 6,242,953 B1
• Filed: 01/10/2000
• Issued: 06/05/2001
• Est. Priority Date: 06/01/1998
• Status: Expired due to Term

• Current Assignee: NVIDIA Corporation
• Original Assignee: 3DFX Interactive Incorporated (NVIDIA Corporation)
• Inventors: Thomas, John C.
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): TRA, ANH QUAN
• Application Number:
  US09/480,325
• Time in Patent Office: 512 Days
• Field of Search: 327/254, 327/258, 327/259, 327/115, 327/117, 377/47, 377/48
• US Class Current: 327/115
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

Multiplexers are used to generate synchronized slave clocks from a common master clock. A first multiplexer and a second multiplexer generate a first slave clock and a second slave clock, respectively, from the common master clock. A third multiplexer and a fourth multiplexer are configured as a divide-by-n circuit for providing a third slave clock that is a divided version of the second slave clock. A fifth multiplexer provides a matching delay to preserve the synchronization between the first slave clock and the other slave clocks. A sixth multiplexer is used to select between the second slave clock and the third slave clock in response to a select signal. A flip-flop may be used to provide the select signal and to guard against false selection of slave clocks.

Claims

1. A synchronization circuit coupled to a source signal, comprising:

a first Q-sync circuit coupled to the source signal for providing a first output signal and a second output signal, the first output signal being a divided copy of the source signal, the second output signal being out of phase with the first output signal by a first predetermined number of degrees, the first Q-sync circuit coupled to a first frequency-divide circuit for receiving a divided copy of the source signal; and

a second Q-sync circuit coupled to the source signal for providing a third output signal and a fourth output signal, the third output signal being out of phase with the second output signal by a second predetermined number of degrees, the fourth output signal being out of phase with the third output signal by a predetermined number of degrees, the second Q-sync circuit coupled to a second frequency-divide circuit for receiving a divided copy of the source signal;

wherein the first and second Q-sync circuits each comprise;

a first selection circuit having a plurality of inputs and an output, a first input coupled to receive an input signal, a second input coupled to the output of the first selection circuit, a third input coupled to a clock; and

a second selection circuit having a plurality of inputs and an output, a first input coupled to receive an inverted input signal, a second input coupled to the output of the second selection circuit, a third input coupled to the clock.

2. The circuit of claim 1, wherein the second output signal is 180 degrees out of phase with the first output signal, the third output signal is 180 degrees out of phase with the second output signal, and the fourth output signal is 90 degrees out of phase with the third output signal.

3. The circuit of claim 1, wherein the first and second frequency-divide circuits are divide-by-2 circuits.

4. The circuit of claim 1, wherein the first and second selection circuits are multiplexers.