Method and system for addressing LCD including thin film diodes

• US 6,243,062 B1
• Filed: 03/06/1998
• Issued: 06/05/2001
• Est. Priority Date: 09/23/1997
• Status: Expired due to Term

• Current Assignee: First Chicago/NBD Bank N.A., InnoLux Corporation
• Original Assignee: OIS Optical Imaging Systems, Inc. (KOCH Industries Incorporated)
• Inventors: den Boer, Willem, Baron, Yair
• Primary Examiner(s): Saras, Steven
• Assistant Examiner(s): ENGLISH, ALECIA DIANE
• Application Number:
  US09/035,819
• Time in Patent Office: 1,187 Days
• Field of Search: 345/96, 345/87, 345/91, 345/210
• US Class Current: 345/91
• CPC Class Codes: G02F 1/1365 in which the switching element is a two-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0895 having more than one selection line for a two-terminal active matrix LCD, e.g. Lechner and D2R circuits
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/367 with a nonlinear element in series with the liquid crystal cell, e.g. a diode, or M.I.M. element

Abstract

A system and method for driving a thin film diode (TFD) inclusive AMLCD or imaging device (e.g. x-ray imager) includes providing each pixel with a pair of select lines and a single data line. Drive schemes are provided which increase the circuits tolerance for spacial and temporal variations in diode (e.g. MIM diode) characteristics, improve response time, increase the circuit'"'"'s tolerance for RC delays on data lines, and reduces the potential for crosstalk or image retention. In certain embodiments, where each pixel includes a pair of select lines, and a single data line, the select voltage on the first select line alternates between V_S+V_offset and V_S−V_offset for subsequent frames, while the select voltage on the other select line alternates between −V_S+V_offset and −V_S−V_offset for subsequent frames, thereby allowing voltage at the common node to be added to the data voltage. Drive schemes herein are used in conjunction with row inversion driving of pixel arrays, and some embodiments are also compatible with column inversion, frame inversion, and/or pixel inversion.

Claims

1. A method of addressing an active matrix liquid crystal display, comprising the steps of:

providing a plurality of pixels, each of the pixels including a liquid crystal layer sandwiched between first and second pixel electrodes;

providing each pixel with first, second, third and fourth thin film MIM diodes (TFDs) of non-linear resistance that are in communication with the first pixel electrode in each pixel, each of said first and second thin film diodes including first and second opposing electrodes with a semi-insulating material provided therebetween, with the first and third MIM diodes being on one side of the common node and the second and fourth MIM diodes in each pixel being on the other side of the common node in the pixel;

providing each pixel with first and second parallel select address lines, the first select address line being in communication with the first and third thin film diode in each pixel and the second select address line being in communication with the second and fourth thin film diode in each pixel;

providing each pixel with a data address line that is in communication with the second pixel electrode in each pixel, the data address lines being perpendicular to the first and second select address lines;

coupling the first, second, third and fourth thin film diodes together at a common node, and in each pixel the liquid crystal layer and the first and second pixel electrodes being positioned electrically between the common node of the pixel and the data address line of the pixel;

in one of the pixels, (i) simultaneously in a first frame applying a first operating potential to the first select address line and a second operating potential to the second select address line, wherein the first and second operating potentials are of substantially equal magnitude but of opposite polarity relative to zero;

after step (i) is performed, (ii) simultaneously in a second frame immediately following the first frame, applying a third operating potential to the first select address line and a fourth operating potential to the second select address line, wherein the third and fourth operating potentials are of substantially equal magnitude but of opposite polarity relative to zero; and

after steps (i) and (ii) are performed, (iii) simultaneously in a third frame immediately following the second frame, applying a fifth operating potential to the first select address line and a sixth operating potential to the second select address line, wherein the fifth and sixth operating potentials are of substantially equal magnitude but of opposite polarity relative to zero;

wherein the steps (i)-(iii) the first, third and fifth operating potentials applied to the first select address line are all of the same polarity relative to zero and the second, fourth, and sixth operating potentials applied to the second select line are of a polarity relative to zero opposite the polarity of the potentials applied to the first select line; and

driving the pixels in the display using a type of inversion so that in a given frame a first group of pixels in the display is driven so that each common node in the first group of pixels has a voltage value greater than the voltage value at a corresponding pixel electrode across the liquid crystal layer therefrom in the pixel, and in said given frame a second group of pixels in the display is driven so that each common node in the second group of pixels has a voltage value less than the voltage value at a corresponding pixel electrode across the liquid crystal layer there from in the pixel.

2. The method of claim 1, wherein said steps (i)-(iii) are performed in order to bias the diodes into an on condition to facilitate the storage of charge in a capacitor in the pixel including the liquid crystal layer and the first and second pixel electrodes;

and, in the pixel, applying charge to the data address line during application of the potentials of opposite polarity to the select address lines in order to store electric charge in said capacitor.

3. The method of claim 1, wherein said first, third, and fifth operating potentials are of substantially the same magnitude, and wherein said second, fourth, and sixth operating potentials are of substantially the same magnitude.

4. The method of claim 1, wherein the inversion is row inversion, whereby the first group of pixels is in a first row of pixels in the display and the second group of pixels is in a second row of pixels in the display, and wherein the first and second groups of pixels are not in the same row of a display.

5. The method of claim 1, wherein the inversion is pixel inversion.

6. A method of addressing a liquid crystal display including thin film diodes, the method comprising the steps of:

providing a plurality of pixels in the display, each of the pixels including a liquid crystal layer and first and second pixel electrodes sandwiching the liquid crystal layer therebetween so as to form a capacitor;

providing each pixel with first and second thin film diodes which are nonlinear resistance elements, said thin film diodes being coupled via a common node, the common node being located electrically between (a) the diodes, and (b) the capacitor;

wherein said first pixel electrode is located electrically between said second pixel electrode and said common node;

providing each pixel with first and second select address lines, the first select address line being coupled to the first thin film diode and the second select address line being coupled to the second thin film diode;

providing each pixel with a data address line;

in a pixel, biasing the first and second thin film diodes into an on condition to facilitate storage of charge in the capacitor of the pixel by in successive frames varying a select voltage applied to the first select address line between V_S+V_offset and V_S−

V_offset, and varying a select voltage applied to the second select address line between −

V_S+V_offset and −

V_S−

V_offset, wherein V_S is one voltage and V_offset is another voltage that is less than V_S;

driving the display via one of (a) row inversion, (b) column inversion, and (c) pixel inversion, so that in a given frame a first group of pixels in the display has a first polarity and a second group of pixels in the display has a second polarity, with the first polarity and second polarity being opposite one another; and

wherein polarity is defined in view of a voltage at the common node relative to a voltage at the second pixel electrode in a particular pixel, so that in said first group of pixels in said given frame the voltage at the common node is greater than the voltage at the second pixel electrode, and in said second group of pixels in said given frame the voltage at the common node is less than the voltage at the second pixel electrode.

7. The method of claim 6, further including applying V_S−

V_offset to the first select address line and applying −

V_S−

V_offset to the second select line, respectively, at the same time, and applying V_S+V_offset to the first select line and −

V_S+V_offset to the second select line at the same time.

8. The method of claim 6, wherein all operating potentials applied to the first select line are greater than zero and all operating potentials applied to the second select line are less than zero.

9. The method of claim 6, further comprising maintaining a substantially constant voltage gap between potentials applied to the first and second select lines, in all frames.

10. The method of claim 6, further comprising the steps of:

applying holding voltages to each of the first and second select lines during non-select periods in order to improve charge retention in the pixel, with the holding voltage being maintained during entire periods between select pulses until the same row is selected again, and wherein adjacent rows have opposite polarity holding voltages compatible with row inversion.

11. The method of claim 10, further comprising maintaining the holding voltages on the first and second select lines during the entire non-select period between pulses, so as to cancel out voltage shift from the first and second MIM diodes.

12. The method of claim 11, further comprising the steps of, at termination of data voltage pulses changing voltages on the first and second select lines by equal magnitude but opposite polarity amounts in order to implement the holding voltages.

13. The method of claim 6, wherein said first and second diodes are metal-insulator-metal (MIM) diodes, and the method further comprising providing each pixel with third and fourth MIM diodes so that each pixel includes four separate MIM diodes, two on each side of the common node in each pixel.

14. A pixel structure including an array of thin film diodes which are non-linear resistance elements, the structure comprising:

an array of pixels;

first and second thin film diodes, each of nonlinear resistance, in each of said pixels;

a common node in each pixel coupling together said first diode and said second diode;

each pixel including first and second parallel select lines, said first select line connected to said first diode in each pixel and said second select line connected to said second diode in each pixel;

each pixel including a data line oriented perpendicular to said first and second select lines of the pixel;

simultaneous offset scan driving means for driving the display in one of (i) a row inversion manner, and (ii) a pixel inversion manner;

the simultaneous offset scan driving means also for charging the pixel so as to supply data to a viewer of the display, said simultaneous offset scan driving means for simultaneously applying, in a first frame, a select voltage of V_S−

V_offset to said first select line and a select voltage of −

V_S−

V_offset to said second select line, and thereafter simultaneously applying, in a second frame subsequent to said first frame, a select voltage of V_S+V_offset to said first select line and a select voltage of −

V_S+V_offset to said second select line.

15. The structure of claim 14, further including means for applying a holding voltage to each of said first and second select lines between pulses, and for maintaining the holding voltage until the same row of pixels is selected again, and wherein adjacent rows of pixels in a given frame have opposite polarity holding voltages.

16. The structure of claim 14, wherein the array of pixels is in a liquid crystal display.

17. The structure of claim 14, wherein the array of pixels is in an imager.