Optimization of a graphics processor system when rendering images

• US 6,243,107 B1
• Filed: 08/10/1998
• Issued: 06/05/2001
• Est. Priority Date: 08/10/1998
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: 3D Labs
• Inventors: Mullis, Donald Wayne, Valtin, Peter Bingham
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US09/131,562
• Time in Patent Office: 1,030 Days
• Field of Search: 345/504, 709/201, 709/105, 709/106, 709/107, 709/108, 709/208, 709/203, 709/207
• US Class Current: 345/506
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

A method and system for optimizing the performance of a graphics processor system is disclosed. The graphics processor system includes multiple CPUs. The system has at least one application thread or master thread, and in addition each CPU is assigned a slave thread. In a first aspect, the method and system comprises assigning each slave to a particular CPU and causing the master thread to move between the processors to cause each slave thread to execute its graphics pipeline. This minimizes data motion due to application inputs being transferred from CPU to CPU. The method and system further includes providing a summary of relevant changes to graphics state to each slave, thus guaranteeing correct state without requiring synchronization around state updates. Accordingly a system and method in accordance with the present invention minimizes data motion during input and also minimizes synchronization associated therewith in a graphics processor system. In a second aspect, the method and system comprises incorporating within each slave thread the entire graphics computation pipeline. Consequently no intermediate outputs are transferred from CPU to CPU, thus minimizing output data motion. The method and system further provides separately addressable output buffers for each slave for communication with the hardware. These output buffers are processed by the hardware in an order corresponding to the original order of inputs. Thus correct serial output is guaranteed with minimal synchronization between threads. Accordingly, a system and method in accordance with the present invention minimizes output data motion and also minimizes synchronization associated therewith in a graphics processor system.

Claims

1. A method for optimizing the performance of a graphics processor system, the graphics processor system including a plurality of processors and a master thread, each of the processors including a slave thread;

the method comprising the steps of;

(a) providing an entire graphics pipeline within each of the slave threads; and

(b) causing the master thread to move between the processors to cause each processor to execute its graphics pipeline, wherein the transfer of data between processors is minimized.

2. The method of claim 1 in which each of the processors include a cache.

3. The method of claim 2 in which each cache includes a substantial portion of the data for the graphics pipeline from its slave thread.

4. The method of claim 3 wherein only an amount of data necessary to establish correct starting conditions for a processor is transferred between processors.

5. The method of claim 4 which further comprises the step of (c) providing an output buffer for each slave thread.

6. The method of claim 5 wherein each slave thread has independent access to the hardware.

7. The method of claim 5 in which the output buffer'"'"'s output data can be deposited for later use by the hardware.

8. The method of claim 5 wherein each output buffer would be reordered to match the original ordering of the input data.

9. A method for optimizing the performance of a graphics processor system, the graphics processor system including a plurality of processors and a master thread, each of the processors including a slave thread;

the method comprising the steps of;

(a) providing an entire graphics pipeline within each of the slave threads;

(b) causing the master thread to move sequentially between the processors to cause each processor to execute its graphics pipeline;

(c) providing a summary of a previous processor state to a subsequent processor, wherein synchronization is minimized.

10. The method of claim 9 wherein each of the processors include a cache.

11. The method of claim 10, in which each cache includes a substantial portion of the data for the graphics pipeline from its slave thread.

12. The method of claim 10 wherein each slave thread has independent access to the hardware output buffer.

13. The method of claim 10 in which the output buffer'"'"'s output data can be deposited for later use by the hardware.

14. The method of claim 9 wherein only an amount of data necessary to establish correct starting conditions for a processor is transferred between processors.

15. The method of claim 9 which further comprises the step of (d) of providing an output buffer for each slave thread.

16. The method of claim 9 wherein each output buffer would be reordered to match the original ordering of the input data.

17. A computer readable medium containing program instructions for optimizing the performance of a graphics processor system, the graphics processor system including a plurality of processors and a master thread, each of the processors including a slave thread;

the program instructions for;

(a) providing an entire graphics pipeline within each of the slave threads; and

(b) causing the master thread to move between the processors to cause each processor to execute its graphics pipeline, wherein the transfer of data between processors is minimized.

18. A computer readable medium containing program instructions for optimizing the performance of a graphics system, the graphics processor system including a plurality of processors and a master thread, each of the processors including a slave thread;

the program instructions for;

(a) providing an entire graphics pipeline within each of the slave threads;

(b) causing the master thread to move sequentially between the processors to cause each processor to execute its graphics pipeline;

(c) providing a summary of a previous processor state to a subsequent processor, wherein synchronization is minimized.

19. A method for optimizing the computation of a multiprocessor system including a master thread, each of the processors within the multiprocessor system including a slave thread;

the method comprising the steps of;

(a) providing an entire pipeline within each of the slave threads; and

(b) causing the master thread to move between the processors to cause each processor to execute its pipeline, wherein the transfer of data between processors is minimized.