Nonvolatile semiconductor memory

• US 6,243,295 B1
• Filed: 03/16/2000
• Issued: 06/05/2001
• Est. Priority Date: 03/19/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Satoh, Shinji
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/526,849
• Time in Patent Office: 446 Days
• Field of Search: 365/185.17, 365/185.24, 365/185.27, 365/185.29, 365/185.33
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory cell in a NAND cell unit is constructed by a main transistor and parasitic transistor, which share a floating gate electrode and control gate electrode, and are connected in series with each other. The parasitic transistor is formed at an edge portion of the main transistor and, more particularly, an edge portion of the floating gate electrode. The threshold value of the parasitic transistor is higher than that of the main transistor. The parasitic transistor is formed in an offset area defined by the space between the edge portion of the floating gate electrode and the source/drain region. The offset area can be provided by forming a spacer on side wall portions of the floating gate electrode and control gate electrode.

Claims

1. A nonvolatile semiconductor memory comprising:

a NAND cell series having one and another ends, and said NAND cell series including a plurality of memory cells connected in series;

a first select gate transistor connected between the one end of said NAND cell series and a bit line; and

a second select gate transistor connected between the another end of said NAND cell series and a source line,

wherein each of the plurality of memory cells consists of a main transistor, and parasitic transistors that sandwich said main transistor, and

said main transistor and said parasitic transistors share a gate electrode, and threshold values of said parasitic transistors are higher than a threshold value of said main transistor.

2. A nonvolatile semiconductor memory according to claim 1, wherein said main transistor is located at a central portion of the gate electrode, and said parasitic transistors are located at edge portions of the gate electrode.

3. A nonvolatile semiconductor memory according to claim 1, wherein offset areas defined by spaces are located between edge portions of the gate electrode and source/drain layers, and

said parasitic transistors are located in said offset areas.

4. A nonvolatile semiconductor memory according to claim 1, wherein offset areas defined by side-wall spaces are located between edge portions of the gate electrode and source/drain layers, and

said parasitic transistors are located in said offset areas.

5. A nonvolatile semiconductor memory according to claim 1, wherein offset areas defined by bird'"'"'s beak insulators are located at edge portions of the gate electrode, and

said parasitic transistors are located in said offset areas.

6. A nonvolatile semiconductor memory according to claim 1, wherein the.gate electrode has a lower portion and an upper portion, a width of the lower portion is narrower than that of the upper portion,

said parasitic transistors are located in offset areas defined by the edge portions.

7. A nonvolatile semiconductor memory according to claim 1, wherein upon a program operation, a memory cell in an erase state of the plurality of memory cells is turned on when a channel is at a ground potential, and is turned off when the channel is at a positive potential.

8. A nonvolatile semiconductor memory according to claim 1, wherein upon a program operation, a channel potential of a program inhibit cell of the plurality of memory cells is boosted by potentials applied to control gate electrodes of the plurality of memory cells.

9. A nonvolatile semiconductor memory according to claim 1, wherein a substrate bias effect of said parasitic transistors is larger than a substrate bias effect of said main transistor.

10. A nonvolatile semiconductor memory according to claim 1, wherein a rate of change in threshold value of the plurality of memory cells due to a substrate bias effect differs between a range where a channel potential is smaller than a predetermined value and a range where the channel potential is larger than the predetermined value.

11. A nonvolatile semiconductor memory according to claim 1, wherein each of the plurality of memory cells stores multi-level data.

12. A nonvolatile semiconductor memory comprising:

a NAND cell series having one and another ends, and said NAND cell series including a plurality of memory cells connected in series;

a first select gate transistor connected between the one end of said NAND cell series and a bit line; and

a second select gate transistor connected between the another end of said NAND cell series and a source line,

wherein each of the plurality of memory cells consists of a main transistor, and a parasitic transistor connected in series with said main transistor, and

said main transistor and said parasitic transistor share a gate electrode, and a threshold value of said parasitic transistor is higher than a threshold value of said main transistor.

13. A nonvolatile semiconductor memory according to claim 12, wherein said parasitic transistor is located on the bit line side of said main transistor.

14. A nonvolatile semiconductor memory according to claim 12, wherein said parasitic transistor is located on the source line side of said main transistor.

15. A nonvolatile semiconductor memory according to claim 12, wherein said main transistor is located at a central portion of the gate electrode, and said parasitic transistor is located at an edge portion of the gate electrode.

16. A nonvolatile semiconductor memory according to claim 12, wherein an offset area defined by a space is located between an edge portion of the gate electrode and a source/drain layer, and

said parasitic transistor is located in said offset area.

17. A nonvolatile semiconductor memory according to claim 12, wherein an offset area defined by a side-wall space is located between an edge portion of the gate electrode and a source/drain layer, and

said parasitic transistor is located in said offset area.

18. A nonvolatile semiconductor memory according to claim 12, wherein an offset area defined by a bird'"'"'s beak insulator is located at an edge portion of the gate electrode, and

said parasitic transistor is located in said offset area.

19. A nonvolatile semiconductor memory according to claim 12, wherein the gate electrode has a lower portion and an upper portion, a width of the lower portion is narrower than that of the upper portion, and

said parasitic transistor is located in an offset area defined by the edge portion.

20. A nonvolatile semiconductor memory according to claim 12, wherein upon a program operation, a memory cell in an erase state of the plurality of memory cells is turned on when a channel is at a ground potential, and is turned off when the channel is at a positive potential.

21. A nonvolatile semiconductor memory according to claim 12, wherein upon a program operation, a channel potential of a program inhibit cell of the plurality of memory cells is boosted by potentials applied to control gate electrodes of the plurality of memory cells.

22. A nonvolatile semiconductor memory according to claim 12, wherein a substrate bias effect of said parasitic transistor is larger than a substrate bias effect of said main transistor.

23. A nonvolatile semiconductor memory according to claim 12, wherein a rate of change in threshold value of the plurality of memory cells due to a substrate bias effect differs between a range where a channel potential is smaller than a predetermined value and a range where the channel potential is larger than the predetermined value.

24. A nonvolatile semiconductor memory according to claim 12, wherein each of the plurality of memory cells stores multi-level data.

25. A nonvolatile semiconductor memory comprising:

a NAND cell series having one and another ends, and said NAND cell series including a plurality of memory cells connected in series;

a first select gate transistor connected between the one end of said NAND cell series and a bit line; and

a second select gate transistor connected between the another end of said NAND cell series and a source line,

wherein at least one of said first and second select gate transistors consists of a main transistor, and parasitic transistors that sandwich said main transistor, and

said main transistor and said parasitic transistors share a gate electrode, and threshold values of said parasitic transistors are higher than a threshold value of said main transistor.

26. A nonvolatile semiconductor memory according to claim 25, wherein said main transistor is located at a central portion of the gate electrode, and said parasitic transistors are located at edge portions of the gate electrode.

27. A nonvolatile semiconductor memory according to claim 25, wherein offset areas defined by spaces are located between edge portions of the gate electrode and source/drain layers, and

said parasitic transistors are located in said offset areas.

28. A nonvolatile semiconductor memory according to claim 25, wherein offset areas defined by side-wall spaces are located between edge portions of the gate electrode and source/drain layers, and

said parasitic transistors are located in said offset areas.

29. A nonvolatile semiconductor memory according to claim 25, wherein offset areas defined by bird'"'"'s beak insulators are located at edge portions of the gate electrode, and

said parasitic transistors are located in said offset areas.

30. A nonvolatile semiconductor memory according to claim 25, wherein the gate electrode has a lower portion and an upper portion, a width of the lower portion is narrower than that of the upper portion, and

said parasitic transistors are located in offset areas defined by the edge portions.

31. A nonvolatile semiconductor memory according to claim 25, wherein upon a program operation, a memory cell in an erase state of the plurality of memory cells is turned on when a channel is at a ground potential, and is turned off when the channel is at a positive potential.

32. A nonvolatile semiconductor memory according to claim 25, wherein upon a program operation, a channel potential of a program inhibit cell of the plurality of memory cells is boosted by potentials applied to control gate electrodes of the plurality of memory cells.

33. A nonvolatile semiconductor memory according to claim 25, wherein a substrate bias effect of said parasitic transistors is larger than a substrate bias effect of said main transistor.

34. A nonvolatile semiconductor memory according to claim 25, wherein a rate of change in threshold value of one of said first and second select gate transistors due to a substrate bias effect differs between a range where a channel potential is smaller than a predetermined value and a range where the channel potential is larger than the predetermined value.

35. A nonvolatile semiconductor memory according to claim 25, wherein each of the plurality of memory cells stores multi-level data.

36. A nonvolatile semiconductor memory comprising:

a NAND cell series having one and another ends, and said NAND cell series including a plurality of memory cells connected in series;

a first select gate transistor connected between the one end of said NAND cell series and a bit line; and

a second select gate transistor connected between the another end of said NAND cell series and a source line,

wherein at least one of said first and second select gate transistors consists of a main transistor, and a parasitic transistor connected in series with said main transistor, and

said main transistor and said parasitic transistor share a gate electrode, and a threshold value of said parasitic transistor is higher than a threshold value of said main transistor.

37. A nonvolatile semiconductor memory according to claim 36, wherein said parasitic transistor is located on the bit line side of said main transistor.

38. A nonvolatile semiconductor memory according to claim 36, wherein said parasitic transistor is located on the source line side of said main transistor.

39. A nonvolatile semiconductor memory according to claim 36, wherein said main transistor is located at a central portion of the gate electrode, and said parasitic transistor is located at an edge portion of the gate electrode.

40. A nonvolatile semiconductor memory according to claim 36, wherein an offset area defined by a space is located between an edge portion of the gate electrode and a source/drain layer, and

said parasitic transistor is located in said offset area.

41. A nonvolatile semiconductor memory according to claim 36, wherein an offset area defined by a side-wall space is located between an edge portion of the gate electrode and a source/drain layer, and

said parasitic transistor is located in said offset area.

42. A nonvolatile semiconductor memory according to claim 36, wherein an offset area defined by a bird'"'"'s beak insulator is located at an edge portion of the gate electrode, and

said parasitic transistor is located in said offset area.

43. A nonvolatile semiconductor memory according to claim 36, wherein the gate electrode has a lower portion and an upper portion, a width of the lower portion is narrower than that of the upper portion, and

said parasitic transistor is located in an offset area defined by the edge portion.

44. A nonvolatile semiconductor memory according to claim 36, wherein upon a program operation, a memory cell in an erase state of the plurality of memory cells is turned on when a channel is at a ground potential, and is turned off when the channel is at a positive potential.

45. A nonvolatile semiconductor memory according to claim 36, wherein upon a program operation, a channel potential of a program inhibit cell of the plurality of memory cells is boosted by potentials applied to control gate electrodes of the plurality of memory cells.

46. A nonvolatile semiconductor memory according to claim 36, wherein a substrate bias effect of said parasitic transistor is larger than a substrate bias effect of said main transistor.

47. A nonvolatile semiconductor memory according to claim 36, wherein a rate of change in threshold value of one of said first and second select gate transistors due to a substrate bias effect differs between a range where a channel potential is smaller than a predetermined value and a range where the channel potential is larger than the predetermined value.

48. A nonvolatile semiconductor memory according to claim 36, wherein each of the plurality of memory cells stores multi-level data.