Compact electrically erasable memory cells and arrays

• US 6,243,296 B1
• Filed: 06/22/1999
• Issued: 06/05/2001
• Est. Priority Date: 10/01/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Sansbury, James D.
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/338,005
• Time in Patent Office: 714 Days
• Field of Search: 365/185.18, 365/185.19, 365/185.23, 365/185.26, 365/185.28
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/38 using tunnel diodes

Abstract

A nonvolatile memory cell (600) has a read device (510), program device (515), and tunnel diode (535). A write control line (WC) is directly coupled to the tunnel diode (535). The memory cell (500) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, half-select voltages are used on the write control (WC) and control gate lines (CG) for unselected memory cells to prevent disturb and minimize oxide stress.

Claims

1. A method of configuring a selected memory cell in an array of memory cells comprising:

providing a first voltage to a first write control line for the selected memory cell, wherein the first write control line is directly coupled to a tunnel diode of the selected memory cell; and

providing a second voltage to a second write control line for an unselected memory cell, wherein the second voltage is a voltage above ground and less than the first voltage, and the second write control line is directly coupled to a tunnel diode of the unselected memory cell.

2. The method of claim 1 wherein the first voltage is VPP.

3. The method of claim 1 wherein the second voltage is in a range from about 8 volts to about 13 volts.

4. The method of claim 1 further comprising:

providing a third voltage to a control gate of the unselected memory cell that is different from the second voltage.

5. The method of claim 4 wherein the third voltage is at a voltage level to prevent disturbing a state of the unselected memory cell.

6. The method of claim 1 wherein the selected memory cell is a floating gate device.

7. The method of claim 1 wherein the selected memory cell is a PMOS floating gate transistor.

8. The method of claim 1 wherein the selected memory cell is a Flash cell.

9. The method of claim 1 wherein the selected memory cell is an EEPROM cell.

10. The method of claim 1 further comprising:

providing a third voltage to a control gate of the selected memory, wherein the third voltage is at a different voltage level than a fourth voltage provided to a tunnel diode of the unselected memory cell.

11. A method of configuring a selected floating gate memory cell in an array of floating gate memory cells comprising coupling a programming voltage to a tunnel diode of the selected memory cell and coupling an intermediate voltage, above ground and below the programming voltage, to a tunnel diode of the unselected memory cell.

12. The method of claim 11 whereby the intermediate voltage prevents disturb of the unselected memory cell while the selected memory cell is being configured.

13. The method of claim 11 wherein the programming voltage is in a range from about 9 volts to about 13 volts.

14. The method of claim 11 wherein the programming voltage is generated on an integrated circuit containing the memory cells.

15. The method of claim 11 wherein the intermediate voltage is generated on an integrated circuit containing the memory cells.

16. The method of claim 11 wherein the selected memory cell is configured by hot-electron programming.

17. The method of claim 11 wherein the selected memory cell is configured by tunneling.

18. The method of claim 11 wherein the memory cells are PMOS transistors.

19. The method of claim 11 wherein the selected memory cell is coupled to a first bit line and the unselected memory cells is coupled to a second bit line.

20. The method of claim 11 wherein the selected memory cell and unselected memory cell are coupled to the same bit line.

21. The method of claim 11 wherein the selected memory cell and unselected memory cell are coupled to different control gate lines.

22. The method of claim 11 wherein the selected memory cell and unselected memory cell are coupled to the same control gate line.

23. The method of claim 11 wherein the intermediate voltage is about half of the programming voltage.