Semiconductor memory device and signal line switching circuit

• US 6,243,301 B1
• Filed: 11/23/1999
• Issued: 06/05/2001
• Est. Priority Date: 11/27/1998
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kuroda, Naoki, Kojima, Makoto, Agata, Masashi
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/447,674
• Time in Patent Office: 560 Days
• Field of Search: 365/189.01, 365/189.02, 365/230.01, 365/230.02, 365/230.06
• US Class Current: 365/189.02
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

Redundancy function with excellent repair efficiency is implemented by specifying a single address for a semiconductor memory device of a multi-bit accessing type. A memory array includes a plurality of memory segments associated with respective addresses. Each memory segment is coupled to a data bus multiplexer via an associated first data bus. A sub-data bus, which includes a larger number of signal lines than that of those included in the first data bus, is provided for each memory segment. These signal lines are connected to associated bit lines in each memory sub-array. A data bus switching circuit is associated with each memory segment to electrically connect the respective signal lines included in the first data bus to the counterparts included in the sub-data bus to meet a predetermined relationship by cutting one of fuses off. In this manner, redundancy function with excellent repair efficiency is implementable on a bit-by-bit basis, not on an address basis.

Claims

1. A semiconductor memory device for accessing a multiplicity of bits at a time responsive to a single address specified, the memory device comprising:

an array of memory cells, which are subdivided into a plurality of memory segments associated with respective addresses, and

an internal data bus having the same bit width as the multiplicity of bits for transferring accessed data, the internal data bus including signal lines each corresponding to a bit of the multiplicity of bits,

wherein each said memory segment includes;

a memory sub-array, and

a sub-data bus having a larger bit width than the multiplicity of bits, the sub-data bus including signal lines each corresponding to a bit within the larger bit width, each of the signal lines being connected to an associated bit line of the memory sub-array, and

wherein the array of memory cells includes connection switching means for connecting the signal lines of the internal data bus to associated ones of the signal lines of the sub-data bus to meet a predetermined relationship.

2. The device of claim 1, wherein the connection switching means disconnects a specific signal line of the sub-data bus from a corresponding signal line of the internal data bus, the specific signal line being associated with a defective bit line or a defective memory cell, the connection switching means shifting connections of signal lines succeeding the specific signal line of the sub-data bus such that signal lines other than the defective signal line of the sub-data bus are connected to the signal lines of the internal data bus.

3. The device of claim 2, wherein the connection switching means comprises:

a plurality of first data buses associated with the respective memory segments;

a plurality of data bus switching circuits provided for the respective memory segments, each said data bus switching circuit electrically connecting the signal lines of the sub-data bus associated with the memory segment to signal lines of the first data bus associated with the memory segment to meet the predetermined relationship; and

a multiplexer for selecting one of the first data buses that is associated with the memory segment specified and connecting a selected one of the first data buses to the internal data bus.

4. The device of claim 3, wherein the sub-data buses are placed in parallel to the first data buses.

5. The device of claim 3, wherein each said memory segment includes a plurality of the memory sub-arrays, and

wherein the bit lines of the respective memory sub-arrays in each said memory segment are connected in common to the signal lines of the sub-data bus in the memory segment.

6. The device of claim 3, wherein each said data bus switching circuit comprises:

a switch section for electrically connecting each signal line of one of the first data buses to an associated signal line of the sub-data bus in an associated memory segment; and

a switch control section including a plurality of fuses connected in series to each other and controlling the switch section based on terminal potentials of the fuses,

wherein in the switch control section, a first-stage one of the fuses is driven by an associated MOS transistor based on a predetermined potential, while each of the other fuses from the second stage on is driven by an associated MOS transistor based on the terminal potential of a previous-stage one of the fuses.

7. The device of claim 6, wherein at least one inverter comprising an MOS transistor is provided between adjacent ones of the fuses in the switch control section.

8. The device of claim 3, wherein each said data bus switching circuit comprises:

a switch section for electrically connecting each signal line of one of the first data buses to an associated signal line of the sub-data bus in an associated memory segment; and

a switch control section for controlling the switch section,

wherein the switch control section includes;

a plurality of control inverters connected in series to each other, a fuse being inserted into a current path between one power supply and the output terminal of each said control inverter; and

means for applying a predetermined drive potential to the input of a first-stage one of the control inverters so as to turn ON an associated MOS transistor on the current path to which the corresponding fuse is inserted,

wherein each of the remaining control inverters from the second stage on is driven with the output of a previous-stage one of the control inverters so as to turn ON the associated MOS transistor on the current path to which the fuse is inserted when the drive potential is applied to the input of the first-stage control inverter with none of the fuses of the control inverters cut off, and

wherein the switch section is controlled based on the outputs of the respective control inverters.

9. A semiconductor memory device for accessing a multiplicity of bits at a time responsive to a single address specified, the memory device comprising:

an array of memory cells, which are subdivided into a plurality of memory segments associated with respective addresses, and

a plurality of first data buses respectively provided for the memory segments for transferring accessed data, each of the data buses having the same bit width as the multiplicity of bits, each of the first data buses including signal lines each corresponding to a bit of the multiplicity of bits,

wherein each said memory segment includes;

a memory sub-array, and

a data bus switching circuit for connecting signal lines of an associated one of the first data buses to bit lines of the memory sub-array to meet a predetermined relationship,

wherein the data bus switching circuit disconnects a specific bit line from a corresponding signal line of the first data bus, the specific bit line being defective or associated with a defective memory cell, the data bus switching circuit shifting connections of bit lines succeeding the specific bit line such that bit lines other than the specific bit line are connected to the signal lines of the first data bus.

10. The device of claim 9, wherein the bit lines of the memory sub-array associated with each said memory segment are placed in parallel to the first data bus associated with the memory segment.

11. The device of claim 9, wherein each said memory segment includes a plurality of the memory sub-arrays, and wherein the data bus switching circuit is provided for each said memory sub-array.

12. The device of claim 9, wherein each said data bus switching circuit comprises:

a switch section for electrically connecting each of the signal lines of the first data bus to associated one of the bit lines; and

a switch control section including a plurality of fuses connected in series to each other and controlling the switch section based on terminal potentials of the fuses,

wherein in the switch control section, a first-stage one of the fuses is driven by an associated MOS transistor based on a predetermined potential, while each of the other fuses from the second stage on is driven by an associated MOS transistor based on the terminal potential of a previous-stage one of the fuses.

13. The device of claim 12, wherein at least one inverter comprising an MOS transistor is provided between adjacent ones of the fuses in the switch control section.

14. The device of claim 9, wherein each said data bus switching circuit comprises:

a switch section for electrically connecting each of the signal lines of the first data bus to associated one of the bit lines; and

a switch control section for controlling the switch section,

wherein the switch control section includes;

a plurality of control inverters connected in series to each other, a fuse being inserted into a current path between one power supply and the output terminal of each said control inverter; and

means for applying a predetermined drive potential to the input of a first-stage one of the control inverters so as to turn ON an associated MOS transistor on the current path to which the corresponding fuse is inserted,

wherein each of the remaining control inverters from the second stage on is driven with the output of a previous-stage one of the control inverters so as to turn ON the associated MOS transistor on the current path to which the fuse is inserted when the drive potential is applied to the input of the first-stage control inverter with none of the fuses of the control inverters cut off, and

wherein the switch section is controlled based on the outputs of the respective control inverters.

15. A signal line switching circuit comprising:

a switch section for electrically connecting each signal line belonging to a first group of signal lines to an associated signal line belonging to a second group of signal lines to meet a predetermined relationship; and

a switch control section including a plurality of fuses connected in series to each other and controlling the switch section based on terminal potentials of the fuses,

wherein in the switch control section, a first-stage one of the fuses is driven by an associated MOS transistor based on a predetermined potential, while each of the other fuses from the second stage on is driven by an associated MOS transistor based on the terminal potential of a previous-stage one of the fuses.

16. The circuit of claim 15, wherein at least one inverter comprising an MOS transistor is provided between adjacent ones of the fuses in the switch control section.

17. The circuit of claim 15, wherein the f irst group consists of a number n of signal lines and the second group consists of a number (n+1) of signal lines, where n is a positive integer, and

wherein the switch section includes an i^th pair of switches, which are provided between the i^th one of the signal lines of the first group and the i^th and (i+1)^st ones of the signal lines of the second group, where i is an integer and 1≦ i≦

n, and

wherein the switch control section controls the i^th pair of switches based on a terminal potential of the i^th-stage one of the fuses.

18. The circuit of claim 15, wherein each said signal line of the first and second groups is composed of a number k of signal lines, where k is an integer equal to or larger than two, and

wherein the first group consists of a number n of signal line sets and the second group consists of a number (n+1) of signal line sets, where n is a positive integer, and

wherein the switch section includes an i^th group of switches, which are provided between the i^th set of the signal lines of the first group and the i^th and (i+1)^st sets of the signal lines of the second group, where i is an integer and 1≦

i≦

n and the i^th group consists of a number 2k of switches, and

wherein the switch control section controls the i^th group of switches based on a terminal potential of the i^th-stage one of the fuses.

19. A signal line switching circuit comprising:

a switching section for electrically connecting each signal line belonging to a first group of signal lines to an associated signal line belonging to a second group of signal lines to meet a predetermined relationship; and

a switch control section for controlling the switch section;

wherein the switch control section includes;

a plurality of control inverters connected in series to each other, a fuse being inserted into a current path between one power supply and the output terminal of each said control inverter; and

means for applying a predetermined drive potential to the input of a first-stage one of the control inverters so as to turn ON an associated MOS transistor on the current path to which the corresponding fuse is inserted,

wherein each of the remaining control inverters from the second stage on is driven with the output of a previous-stage one of the control inverters so as to turn ON the associated MOS transistor on the current path to which the fuse is inserted when the drive potential is applied to the input of the first-stage control inverter with none of the fuses of the control inverters cut off, and

wherein the switch section is controlled based on the outputs of the respective control inverters.

20. The circuit of claim 19, wherein the first group consists of a number n of signal lines and the second group consists of a number (n+1) of signal lines, where n is a positive integer, and

wherein the switch section includes an i^th pair of switches, which are provided between the i^th one of the signal lines of the first group and the i^th and (i+1)^st ones of the signal lines of the second group, where i is an integer and 1≦ i≦

n, and

wherein the switch control section controls the i^th pair of switches based on the output of the i^th-Stage one of the control inverters.

21. The circuit of claim 19, wherein the potential applying means applies a predetermined initializing potential to the input of the first-stage control inverter so as to turn ON an MOS transistor on a current path between the other power supply, which is more distant from the fuse inserted, and the output terminal of the control inverter, and

wherein the switch control section includes a plurality of latch circuits associated with the respective control inverters, each said latch circuit latching, as the initializing potential thereof, the output of the first-stage control inverter to which the initializing potential is applied as an input.