Dynamic buffer allocation for a computer system

• US 6,243,769 B1
• Filed: 07/18/1997
• Issued: 06/05/2001
• Est. Priority Date: 07/18/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rooney, Jeffrey Jay
• Primary Examiner(s): Le, Dieu-Minh
• Assistant Examiner(s): VO, TIM T
• Application Number:
  US08/896,936
• Time in Patent Office: 1,418 Days
• Field of Search: 395/280, 395/281, 395/876, 395/308, 395/842, 710/100, 710/101, 710/128, 710/22, 710/1, 710/3, 710/4, 710/7, 710/20, 710/21, 710/23, 710/56, 710/52
• US Class Current: 710/56
• CPC Class Codes: G06F 2205/066 User-programmable number or size of buffers, i.e. number of separate buffers or their size can be allocated freely
• CPC Class Codes: G06F 2205/067 Bidirectional FIFO, i.e. system allowing data transfer in two directions
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Abstract

A method for dynamically allocating buffers between components in a computer system is described. Matched sets of bidirectional buffers are used to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.

Claims

1. In a computer system, a method for concurrently transferring data between a processor and a plurality of peripheral devices via a dynamic buffer allocation system comprising a plurality of address buffers and a plurality of data buffers, wherein each of said plurality of address buffers is exclusively associated with one of said plurality of data buffers, the method comprising the acts of:

latching a processor write request comprising an address location in a first peripheral device into a first address buffer of the dynamic buffer allocation system;

latching a processor read request comprising an address location to be read from a second peripheral device into a second address buffer of the dynamic buffer allocation system;

sending said processor read request from said second address buffer to said second peripheral device; and

concurrently transferring data from said processor to a first data buffer of the dynamic buffer allocation system associated with said first address buffer and from said second peripheral device to a second data buffer of the dynamic buffer allocation system associated with said second address buffer.

2. The method of claim 1, further comprising concurrently transferring data from said first data buffer to said first peripheral device and from said second data buffer to said processor.

3. The method of claim 1, wherein said method for concurrently transferring data between a processor and a plurality of peripheral devices comprises transferring data between an Intel Pentium®

Pro processor and a plurality of peripheral devices.

4. The method of claim 1, wherein said method for concurrently transferring data between a processor and a plurality of peripheral devices comprises transferring data between a processor and first and second Peripheral Component Interconnect (PCI) devices.

5. The method of claim 1, wherein said method for concurrently transferring data between a processor and a plurality of peripheral devices comprises transferring data across a processor bus.

6. The method of claim 1, wherein said method for concurrently transferring data between a processor and a plurality of peripheral devices comprises transferring data across a peripheral bus.

7. The method of claim 6, wherein said method for concurrently transferring data between a processor and a plurality of peripheral devices comprises transferring data across a Peripheral Component Interconnect (PCI) bus.

8. In a computer system, a method for concurrently transferring data between a processor and a peripheral device, comprising the acts of:

transferring a first address from a processor to a first buffer;

transferring said first address to a peripheral device;

transferring data from said peripheral device to a second buffer in response to said first address, said second buffer being matched with said first buffer; and

transferring said data from said second buffer to said processor while a second address is transferred from said processor to said first buffer,

wherein said first buffer, and said second buffer, are part of a dynamic buffer allocation system.

9. The method of claim 8, further comprising the acts of:

transferring a third address to a third buffer from said peripheral device;

transferring said third address to said processor;

transferring said second address to said peripheral device;

concurrently transferring data from said processor to a fourth buffer, said fourth buffer being matched with said third buffer, and transferring data from said peripheral device to said second buffer.

10. The method of claim 8, wherein said method for concurrently transferring data between a processor and a peripheral device comprises transferring data between a processor and a Peripheral Component Interconnect (PCI) device.

11. The method of claim 8, wherein said method for concurrently transferring data between a processor and a peripheral device comprises transferring data across a processor bus.

12. The method of claim 8, wherein said method for concurrently transferring data between a processor and a peripheral device comprises transferring data across a peripheral bus.

13. The method of claim 12, wherein said method for concurrently transferring data between a processor and a peripheral device comprises transferring data across a Peripheral Component Interconnect (PCI) bus.