Protocol for arbitrating access to a shared memory area using historical state information

• US 6,243,793 B1
• Filed: 07/25/1997
• Issued: 06/05/2001
• Est. Priority Date: 07/27/1995
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Knauerhase, Robert C., Stanley, James C., Aucsmith, David W.
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/906,134
• Time in Patent Office: 1,411 Days
• Field of Search: 711/152, 711/151
• US Class Current: 711/151
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A method and apparatus for arbitrating access to a shared memory is disclosed. A memory marking unit in the shared memory is read to determine whether the shared memory is currently being accessed by another processor. If the shared memory is not being accessed by another processor, a processor seeking access is granted access. The processor changes the contents of the memory marking unit to lock out other processors from the shared memory. The last task performed on the shared memory space is identified and used to determine whether a task with high priority exists. If a task with high priority exists, the task is performed. If a task with high priority does not exist, the processor having access to the shared memory space accesses the shared memory space for its intended purpose. After the processor is finished accessing the shared memory space, it records the identity of the task performed and unlocks the shared memory space.

Claims

1. A memory unit comprising:

a memory cell that stores data;

an access indication unit, coupled to the memory cell, that records an identity of a first processor accessing the memory cell;

a semaphore unit, coupled to the access indication unit, that prevents a second processor from accessing the memory cell while the identity of the first processor is recorded in the access indication unit; and

a state recorder unit, coupled to the access indication unit, that records state information written by the first processor, the state recorder unit to provide a task last performed on the memory cell to a state engine which determines next tasks that may be performed on the memory cell.

2. The memory unit of claim 1 further comprising an arbitration unit, coupled to the access indication unit, that allows access of the memory cell to one processor at a time.

3. The memory unit of claim 1, wherein the access indication unit comprises a register.

4. The memory unit of claim 1, wherein the state recorder unit comprises a register.

5. A computer system comprising:

a bus;

a first processor coupled to the bus;

a second processor;

a shared memory unit comprising a memory cell that stores data, an access indication unit, coupled to the memory cell, that records an identity of the first processor accessing the memory cell, a semaphore unit, coupled to the access indication unit, that prevents the second processor from accessing the memory cell while the identity of the first processor is recorded in the access indication unit, and a state recorder unit, coupled to the access indication unit, that records state information written by the first processor, the state recorder unit to provide a task last performed on the memory cell to a first state engine which determines next tasks that may be performed on the memory cell.

6. The computer system in claim 5 further comprising:

a second state engine that instructs the second processor how to process data in the memory cell in response to reading the state information recorded in the state recording unit.

7. The computer system in claim 5 further comprising a monitoring unit, coupled to the state recorder unit, the monitoring unit monitoring the state information and sending an interrupt signal to the first processor that starts the first state engine when there is a change in the state information.

8. The computer system in claim 5 further comprising a polling unit, coupled to the state recorder unit, the polling unit monitoring the state recording unit after a predetermined amount of time and starting the first state engine when the polling unit detects a change in the state information.

9. The method of arbitrating access of a shared memory between a plurality of processors, comprising:

determining whether the shared memory is being accessed;

identifying a state of the shared memory, the state indicative of a task last performed;

determining next tasks that may be performed on the shared memory based upon the state of the shared memory; and

granting access of the shared memory to a processor of the plurality of processors designated to perform one of the next tasks.

10. The method of claim 9, wherein determining whether the shared memory is being accessed is achieved by reading the contents of a semaphore register.

11. The method of claim 9, wherein identifying the state of the shared memory is achieved by reading state information in a state recording unit.

12. The method of claim 9, wherein determining the next tasks that may be performed on the shared memory is achieved by checking a next state in a state machine.

13. A computer system comprising:

a bus;

a first processor coupled to the bus;

a second processor;

a shared memory unit comprising a memory cell that stores data, an access indication unit, coupled to the memory cell, that records an identity of the first processor accessing the memory cell, a semaphore unit, coupled to the access indication unit, that prevents the second processor from accessing the memory cell while the identity of the first processor is recorded in the access indication unit, and a state recorder unit, coupled to the access indication unit, that records state information written by the first processor that is indicative of a task last performed on the memory cell, the task performed allowing a state engine to determine one or more next tasks to be performed on the memory cell.