Economical silicon-on-silicon hybrid wafer assembly

• US 6,245,161 B1
• Filed: 02/19/1998
• Issued: 06/12/2001
• Est. Priority Date: 05/12/1997
• Status: Expired due to Term

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: Henley, Francois J., Cheung, Nathan W.
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): Thompson, Craig
• Application Number:
  US09/026,116
• Time in Patent Office: 1,209 Days
• Field of Search: 148/33.2, 148/33.3, 148/33.4, 148/33.5, 438/455, 438/458, 438/459, 438/514, 438/518, 438/526, 438/530, 438/531, 438/977
• US Class Current: 148/33.4
• CPC Class Codes: B81C 1/0038 Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
• CPC Class Codes: B81C 2201/0191 Transfer of a layer from a carrier wafer to a device wafer
• CPC Class Codes: B81C 2201/0192 by cleaving the carrier wafer
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off
• CPC Class Codes: Y10S 117/915 Separating from substrate
• CPC Class Codes: Y10S 156/93 Semiconductive product delaminating, e.g. delaminating emiconductive wafer from underlayer
• CPC Class Codes: Y10S 438/974 Substrate surface preparation
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate
• CPC Class Codes: Y10T 156/11 Methods of delaminating, per se; i.e. , separating at bonding face
• CPC Class Codes: Y10T 156/1158 Electromagnetic radiation applied to work for delamination [e.g., microwave, uv, ir, etc.]
• CPC Class Codes: Y10T 156/19 Delaminating means
• CPC Class Codes: Y10T 428/21 Circular sheet or circular blank
• CPC Class Codes: Y10T 428/24893 : including particulate material
• CPC Class Codes: Y10T 428/249956 : Void-containing component is inorganic

Abstract

An economical hybrid wafer utilizing a lower-quality, lower cost transfer substrate to support a higher-quality thin film. A high-quality thin film (2101) is separated from a donor wafer (2100) and bonded to a transfer, or target, substrate (46). The donor wafer is preferably single-crystal silicon optimized for device fabrication, while the transfer substrate provides mechanical support. The thin film is not grown on the transfer substrate, and thus defects in the transfer substrate are not grown into the thin film. A low-temperature bonding process can provide an abrupt junction between the target wafer and the thin film.

Claims

1. A hybrid silicon wafer assembly, said assembly comprising:

a high-quality single-crystal silicon thin film coupled to a lower-quality silicon transfer substrate.

2. The assembly of claim 1 wherein the high-quality single-crystal silicon thin film is bonded to the lower-quality silicon transfer substrate.

3. The assembly of claim 1 wherein the lower-quality silicon transfer substrate comprises polysilicon.

4. The assembly of claim 1 wherein the lower-quality transfer substrate comprises single-crystal silicon, the high-quality single crystal silicon thin film having a first defect density at least ten times less than a second defect density of the lower-quality substrate.

5. The assembly of claim 4 wherein the first defect density and the second defect densities include dislocation densities.

6. The assembly of claim 1 wherein the lower-quality transfer substrate has a first minority carrier lifetime at least ten times less than a second minority carrier lifetime in the high-quality single-crystal thin film.

7. The assembly of claim 1 wherein the lower-quality transfer substrate has a first carrier mobility at least ten times less than a second carrier mobility in the high-quality single-crystal thin film.

8. The assembly of claim 1 further comprising an adhesion layer disposed between the high-quality single-crystal silicon thin film and the lower-quality silicon transfer substrate.

9. The assembly of claim 8 wherein the adhesion layer comprises a silicide-forming metal.

10. The assembly of claim 9 wherein the silicide-forming metal includes titanium.

11. The assembly of claim 9 wherein the adhesion layer comprises tungsten.

12. The assembly of claim 8 wherein the adhesion layer comprises an oxide.

13. The assembly of claim 1 further comprising a barrier layer disposed between the high-quality single-crystal silicon thin film and the lower-quality silicon transfer substrate.

14. The assembly of claim 13 wherein the barrier layer comprises a silicide-forming metal.

15. The assembly of claim 14 wherein the barrier layer comprises titanium.

16. The assembly of claim 14 wherein the barrier layer comprises tungsten.

17. The assembly of claim 13 wherein the barrier layer comprises an oxide.

18. The assembly of claim 13 further comprising a gettering layer disposed between the barrier layer and the high-quality single-crystal silicon thin film.

19. The assembly of claim 18 wherein the gettering layer comprises polysilicon.

20. The assembly of claim 18 wherein the gettering layer comprises silicon-germanium.