Techniques for wafer level molding of underfill encapsulant

• US 6,245,595 B1
• Filed: 07/22/1999
• Issued: 06/12/2001
• Est. Priority Date: 07/22/1999
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Warner, Ethan, Mostafazadeh, Shahram, Nguyen, Luu, Takiar, Hem P., Smith, Joseph O.
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): Pyonin, Adam
• Application Number:
  US09/359,074
• Time in Patent Office: 691 Days
• Field of Search: 438/26, 438/106, 438/108, 438/112, 438/114, 438/127, 228/180.22
• US Class Current: 438/108
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/67126 Apparatus for sealing, encapsulating, glassing, decapsulating or the like processes H01L23/02, H01L23/28
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/73104 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83856 Pre-cured adhesive, i.e. B-stage adhesive
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method and apparatus for forming a layer of underfill encapsulant on an integrated circuit located on a wafer are described. As a flip chip, the integrated circuit has electrically conductive pads, most of which have a solder ball attached thereto. Most of the solder balls have been flattened in order to provide an enlarged solder wetting area. A layer of underfill encapsulant is injected onto the integrated circuit under pressure to form a layer of underfill encapsulant that is then pre-cured. The integrated circuit is mounted to a substrate and the substrate and the integrated circuit are electrically coupled by a solder reflow operation which also finally cures the underfill encapsulant.

Claims

1. A method for forming a layer of underfill encapsulant on an integrated circuit having an active surface that includes electrically conductive pads selected ones of which have a solder ball bonded thereto, comprising:

flattening a portion of most of the solder balls;

forming a pre-cured layer of underfill encapsulant having a dual stage curing chemistry that includes a pre-cure stage and a final cure stage on the active surface of the integrated circuit such that the flattened solder ball is covered by the pre-cured encapsulant in such a manner that the flattened portion is substantially free of the pre-cured encapsulant; and

reflowing the flattened solder balls so as to final cure the underfill encapsulant during the final cure stage such that there are substantially no voided regions between the substrate and the flip chip integrated circuit such that there is substantially no segregation of the layer of underfill encapsulant.

2. A method as recited in claim 1, wherein the integrated circuit is a flip chip integrated circuit located on a wafer having flip chip bond pads for electrically coupling the flip chip integrated circuit to external circuitry.

3. A method as recited in claim 1, wherein the flattening comprises:

placing a resilient film coplanar to the active surface and in direct contact with the solder ball; and

providing a force to the resilient film normal to the active surface.

4. A method as recited in claim 3, further comprising:

providing a mold having a mold cavity portion suitably arranged to receive the wafer and the encapsulant;

placing the wafer and the resilient film in the mold cavity portion; and

clamping an enclosing portion of the mold on to the mold cavity portion thereby enclosing the wafer and the film in the mold cavity portion.

5. A method as recited in claim 4, where the clamping the enclosing portion provides the force to the resilient film normal to the active surface so that the solder ball is flattened in such a way that a solder ball footprint corresponding to the flattened solder ball is substantially enlarged thereby increasing available solder wetting area.

6. A method as recited in claim 5, wherein the forming the encapsulation layer comprises injecting encapsulant under pressure into the mold cavity.

7. A method as recited in claim 6, wherein the enclosing portion of the mold includes indentations each of which corresponds to and directly aligns with a corresponding saw street on the active surface such that each of the indentations form a corresponding groove in the layer of encapsulant suitable for identifying the corresponding saw street.

8. A method as recited in claim 7, further comprising:

singulating the flip chip integrated circuit.

9. A method as recited in claim 8, wherein the singulating comprises:

wafer sawing the flip chip integrated circuit.

10. A method as recited in claim 8, wherein the singulating comprises:

laser cutting the flip chip integrated circuit.

11. A method as recited in claim 10, further comprising:

aligning the singulated flip chip integrated circuit to a substrate such that selected ones of the flip chip bond pads having flattened solder balls are directly aligned to corresponding substrate bond pads included on the substrate; and

mounting the flip chip integrated circuit on the substrate such that each of the selected flip chip bond pads are in direct contact with the corresponding substrate bond pad.

12. A method as recited in claim 11, wherein the underfill encapsulant is selected from the group comprising:

epoxies, polyimides, and silicon-polyimide copolymers.

13. A method for forming a layer of underfill encapsulant on an integrated circuit having an active surface that includes electrically conductive pads wherein selected ones of the pads each have a solder ball connected thereto, comprising:

flattening the solder balls by,

placing a resilient film coplanar to the active surface and in direct contact with the solder balls, and

providing a force to the resilient film normal to the active surface so that the solder balls are flattened in such a way that a solder ball footprint corresponding to the flattened solder balls is substantially enlarged thereby increasing available solder wetting area;

forming the layer of underfill encapsulant having a dual stage curing chemistry that includes a pre-cure stage and a final cure stage on the active surface of the integrated circuit, wherein a flattened portion of the solder balls remain substantially free of encapsulant by,

providing a mold having a mold cavity portion suitably arranged to receive the wafer and the encapsulant;

placing the wafer and the resilient film in the mold cavity portion;

clamping an enclosing portion of the mold on to the mold cavity portion thereby enclosing the wafer and the film in the mold cavity portion;

injecting the underfill encapsulant under pressure into the mold cavity, pre-curing the injected underfill encapsulant during the pre-cure stage; and

reflowing the solder balls so as to final cure the underfill encapsulant during the final cure stage such that there are substantially no voided regions in the layer of underfill encapsulant.

14. A method as recited in claim 13, wherein the integrated circuit is a flip chip integrated circuit having flip chip bond pads for electrically coupling the flip chip integrated circuit to external circuitry.

15. A method as recited in claim 14, further comprising:

aligning the flip chip bond pads having flattened solder balls to corresponding substrate bond pads included on a substrate; and

mounting the flip chip integrated circuit on the substrate such that each of the flip chip bond pads is in direct contact with the corresponding substrate bond pad.