Method of producing an interconnect structure for an integrated circuit

• US 6,245,662 B1
• Filed: 07/23/1998
• Issued: 06/12/2001
• Est. Priority Date: 07/23/1998
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Naik, Mehul, Broydo, Samuel
• Primary Examiner(s): Trinh, Michael
• Assistant Examiner(s): GUERRERO, MARIA F
• Application Number:
  US09/122,080
• Time in Patent Office: 1,055 Days
• Field of Search: 438/622, 438/634, 438/637, 438/638, 438/641
• US Class Current: 438/622
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material

Abstract

A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

Claims

1. A method of forming an interconnect structure comprising the steps of:

(a) depositing a first insulator layer upon a substrate;

(b) depositing an etch stop layer upon said first insulator layer;

(c) depositing a second insulator layer on top of said etch stop layer;

(d) forming a first mask atop of said second insulator layer;

(e) etching said first insulator layer, said etch stop layer and said second insulator layer in a single step to define a via;

(f) removing said first mask;

(g) forming a second mask to define a trench;

(h) etching said second insulator layer as defined by said second mask to form a trench; and

(i) metalizing said via and said trench to form an interconnect structure.

2. The method of claim 1 wherein said first mask is formed by the following steps:

applying a photoresist material onto said second insulator layer;

developing said photoresist; and

patterning said photoresist to define a location and dimension of said via.

3. The method of claim 1 wherein said etching step which forms said via is a reactive ion etch.

4. The method of claim 1 wherein said etch of said trench in the second insulator layer is a reactive ion etch.

5. The method of claim 1 wherein said first insulator layer and said second insulator layer are made of silicon dioxide.

6. The method of claim 1 wherein said first insulator layer or said second insulator layer or both are made of a low dielectric constant material.

7. The method of claim 1 further comprising forming a second level of interconnect structure containing a second via and a second trench by passivating said metallization and then repeating steps (a) through (h), then etching a passivation layer to expose said metallization at a bottom of said second via and metalizing said second via and trench.

8. The method of claim 1 wherein the etching performed in step (e) is conducted using one etch chemistry.

9. The method of claim 1 wherein said second mask is formed by following steps:

applying a photoresist material onto said second insulator layer;

developing said photoresist; and

patterning said photoresist to define a location and dimension of said trench.

10. The method of claim 9 wherein the photoresist is not developed completely within said via.

12. The method of claim 10 wherein said first mask is formed by the following steps:

applying a photoresist material onto said second insulator layer;

developing said photoresist; and

patterning said photoresist to define a location and dimension of said via.

11. A method of forming a multiple level interconnect structure comprising the steps of:

(a) depositing a first insulator layer upon a substrate;

(b) depositing an etch stop layer upon said first insulator layer;

(c) depositing a second insulator layer on top of said etch stop layer;

(d) forming a first mask atop of said second insulator layer;

(e) etching said first insulator layer, said etch stop layer and said second insulator layer in a single step to define a via;

(f) removing said first mask;

(g) forming a second mask to define a trench;

(h) etching said second insulator layer as defined by said second mask to form a trench;

(i) metalizing said via and said trench to form an interconnect structure;

(j) plagiarizing said metallization;

(k) forming a passivation layer over said planarized metallization;

(l) repeating steps (a)-(h) to form a second level of interconnect structure contains a second via and second trench;

(m) removing said passivation layer at a bottom of said second via; and

(n) metalizing said second via and said second trench to form a second layer for said interconnect structure.

13. The method of claim 11 wherein said etching step which forms said via is a combination of a reactive ion etch and an isotropic etch.

14. The method of claim 11 wherein said etch of said trench in the second insulator layer is a reactive ion etch.

15. The method of claim 11 wherein said first insulator layer and said second insulator layer are made of silicon dioxide.

16. The method of claim 11 wherein said first insulator layer or said second insulator layer or both are made of a low dielectric constant material.

17. The method of claim 11 wherein the etching performed in step (e) is conducted using one etch chemistry.

18. The method of claim 11 wherein said second mask is formed by the following steps:

applying a photoresist material onto said second insulator layer;

developing said photoresist; and

patterning said photoresist to define a location and dimension of said trench.

19. The method of claim 18 wherein the photoresist is not developed completely within said via.