Backside chemical etching and polishing

• US 6,245,677 B1
• Filed: 07/28/1999
• Issued: 06/12/2001
• Est. Priority Date: 07/28/1999
• Status: Expired due to Fees

• Current Assignee: Noor Haq
• Original Assignee: Noor Haq
• Inventors: Haq, Noor
• Primary Examiner(s): Utech, Benjamin L.
• Assistant Examiner(s): PEREZ RAMOS, VANESSA
• Application Number:
  US09/363,295
• Time in Patent Office: 685 Days
• Field of Search: 438/689, 438/690, 438/691, 438/692
• US Class Current: 438/690
• CPC Class Codes: B24B 37/042 operating processes therefor
• CPC Class Codes: H01L 21/02019 Chemical etching
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

Abstract

A process for backside chemical etching and polishing of substrates including the steps of protecting the front surface of the wafer, chemical etching, first dump rinse/spin dry, backside polishing, residue cleaning, second dump rinse/spin dry, and front surface protection removal. The process is generally intended to be used for semiconductor wafers, but it can also be used for processing other types of substrates such as GaAs, GaP, GaAlAs, GaAlP, ceramics, quartz, bonded silicon wafers, dielectric isolated wafers and substrates, etc.

Claims

1. A process for reducing stresses in wafers utilizing backside chemical etching and backside polishing comprising:

a) applying a protective means to a front surface of a wafer, said wafer having been processed such that a front surface of said wafer comprises a plurality of defined chips, each of said chips comprising live circuits defined thereon,

b) chemical etching a backside of the wafer,

c) subjecting the wafer to a first dump rinse/spin dry operation,

d) backside polishing the wafer,

e) removing residue generated during the backside polishing operation from the wafer,

f) subjecting the wafer to a second dump rinse/spin dry operation, and

g) removing said protective means from the front surface of the wafer.

2. The process defined in claim 1 wherein:

said protective means comprises photoresist, polyamide coating materials, wax, or wafer grinding tape.

3. The process defined in claim 1 wherein:

an etchant utilized in said chemical etching process step comprises a mixture of nitric acid, hydrofluoric acid, and acetic acid.

4. The process defined in claim 1 wherein:

an etchant utilized in said chemical etching process step comprises potassium hydroxide.

5. The process defined in claim 1 wherein:

the wafer is exposed to an etchant in the chemical etching process for 5 minutes to 60 minutes.

6. The process defined in claim 1 wherein:

said removing residue generated during the backside polishing operation process step comprises DI water scrubbing, DI water ultrasonic or megasonic cleaning, TCA cleaning, solvent cleaning, or SCI (NH₄OH;

H₂O₂) cleaning.

7. A process for reducing stresses in wafers comprising:

a) applying a protective means to a front surface of a wafer, said wafer having been processed such that a front surface of said wafer comprises a plurality of defined chips, each of said chips comprising live circuits defined thereon,

b) chemical etching a backside of the wafer,

c) subjecting the wafer to a first dump rinse/spin dry operation, and

d) removing said protective means from the front surface of the wafer.

8. The process defined in claim 7 wherein:

said protective means comprises photoresist, polyamide coating materials, wax, or wafer grinding tape.

9. The process defined in claim 7 wherein:

an etchant utilized in said chemical etching process step comprises a mixture of nitric acid, hydrofluoric acid, and acetic acid.

10. The process defined in claim 7 wherein:

an etchant utilized in said chemical etching process step comprises potassium hydroxide.

11. The process defined in claim 7 wherein:

the wafer is exposed to an etchant in the chemical etching process for 5 minutes to 60 minutes.

12. A process for reducing stresses in wafers comprising:

a) applying a protective means to a front surface of a wafer, said wafer having been processed such that a front surface of said wafer comprises a plurality of defined chips, each of said chips comprising live circuits defined thereon,

b) backside polishing the wafer,

c) removing residue generated during the backside polishing operation from the wafer,

d) subjecting the wafer to a dump rinse/spin dry operation, and

e) removing said protective means from the front surface of the wafer.

13. The process defined in claim 12 wherein:

said protective means comprises photoresist, polyamide coating materials, wax, or wafer grinding tape.

14. The process defined in claim 12 wherein:

said removing residue generated during the backside polishing operation process step comprises DI water scrubbing, DI water ultrasonic or megasonic cleaning, TCA cleaning, solvent cleaning, or SCI (NH₄OH;

H₂O₂) cleaning.