Semiconductor package having a heat sink with an exposed surface

• US 6,246,115 B1
• Filed: 10/21/1999
• Issued: 06/12/2001
• Est. Priority Date: 10/21/1998
• Status: Expired due to Term

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Tang, Tom, Chiang, Kevin, Huang, Chien Ping, Lai, Jeng-Yuan, Tien, Candy, Liu, Vicky
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/425,145
• Time in Patent Office: 600 Days
• Field of Search: 257/706, 257/704, 257/675, 257/712, 257/713, 257/717, 257/720, 257/738, 257/737, 257/734, 257/777, 257/778, 257/796, 257/787, 257/797, 257/723, 438/125, 438/122
• US Class Current: 257/706
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19041 being a capacitor

Abstract

An integrated circuit package with a fully-exposed heat sink is provided. The integrated circuit package includes a substrate having a first side being formed with first conductive traces and a second side being formed with second conductive traces. At least one chip is mounted on the substrate and electrically connected to the first conductive traces. A plurality of solder balls are provided at the terminal ends of the second conductive traces to allow external connection of the chip. The fully-exposed heat sink is mounted on the substrate. The heat sink is formed with a plurality of supportive legs arranged in such a manner as to allow a bottom surface of the heat sink to be separated from the chip and a top surface of the heat sink to be tightly attached to a cavity in a mold used to form an encapsulant for enclosing the chip. A plurality of positioning tongues are formed on the heat sink for securing the heat sink in position when performing a molding process for forming the encapsulant. With this integrated circuit package, no jig is required in the assembly of the integrated circuit package. Moreover, since there is no need to use adhesives to adhere the supportive legs onto the substrate, the integrated circuit package would not suffer from delamination as in the case of the prior art. The fully-exposed heat sink allows an increased heat-dissipating efficient as compared to the prior art.

Claims

1. An integrated circuit package, which comprises:

a substrate having a first side and a second side opposing the first side;

first conductive traces formed on the first side of the substrate;

second conductive traces formed on the second side of the substrate, which is electrically connected to the first conductive traces;

at least one chip, which is mounted on the first side of the substrate and electrically connected to the first conductive traces;

a plurality of solder balls provided at the terminal ends of the second conductive traces to allow external connection of the chip;

a heat sink mounted on the first side of the substrate and, being formed with a plurality of supporting legs downwardly extending from sides of the heat sink and arranged in such a manner as to allow a bottom surface of the heat sink to be separated from the chip and a top surface of the heat sink to be tightly attached to a top wall of a cavity in a mold;

a plurality of positioning tongues formed on the heat sink for securing the heat sink in position when performing a molding process; and

an encapsulant which hermetically encloses the chip and part of the heat sink therein in a manner that the top surface of the heat sink is exposed to the outside of the encapsulant.

2. The integrated circuit package of claim 1, wherein the supportive legs are integrally formed with the heat sink and arranged on sides of the heat sink.

3. The integrated circuit package of claim 2, wherein the supportive legs are each formed with a hole to help enforce the bonding between the heat sink and the encapsulant.

4. The integrated circuit package of claim 1, wherein the heat sink is further formed with a plurality of openings each being used for receiving an injection pin of the mold for use in the molding process.

5. The integrated circuit package of claim 4, wherein the openings in the heat sink are formed near the corners of the heat sink.

6. The integrated circuit package of claim 4, wherein the openings in the heat sink are each formed with a toothed inner wall.

7. The integrated circuit package of claim 1, wherein the edge of the heat sink is formed with at least a recessed portion.

8. The integrated circuit package of claim 1, wherein the heat sink is formed in such a manner that the distance from a bottom of each of the supportive legs to the top side of the heat sink is greater than the depth of the cavity in the mold used to form the encapsulant.

9. The integrated circuit package of claim 1, wherein the chip is electrically connected to the first conductive traces via a plurality of gold wires.

10. The integrated circuit package of claim 1, wherein the chip is electrically connected to the first conductive traces by using flip-chip technology.

11. The integrated circuit package of claim 1, wherein the substrate is formed with a plurality of conductive vias to electrically interconnect the first conductive traces and the second conductive traces.

12. The integrated circuit package of claim 1, wherein the gap between the sides of the heat sink and the outer walls of the encapsulant is no greater than 0.1 mm.

13. The integrated circuit package of claim 1, wherein the heat sink is made of a heat-conductive material selected from the group consisting of copper, copper alloy, aluminum, and aluminum alloy.

14. The integrated circuit package of claim 1, wherein the heat sink is secured to the substrate without use of an adhesive.