Low dielectric semiconductor device with rigid, conductively lined interconnection system

• US 6,246,118 B1
• Filed: 02/18/1999
• Issued: 06/12/2001
• Est. Priority Date: 02/18/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Buynoski, Matthew S.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US09/252,185
• Time in Patent Office: 845 Days
• Field of Search: 257/58, 257/76, 257/68--70
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 23/4821 Bridge structure with air gap
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01076 Osmium [Os]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/30105 Capacitance

Abstract

Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid, conductive lining, such as, a hard metal, e.g., W, Mo, Os, Ir or alloys thereof. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, electroplating or electroless plating the hard metal to line the interconnection system and forming dielectric protective layers, e.g., a silane derived oxide bottommost protective layer, on the uppermost metallization level.

Claims

1. A semiconductor device comprising:

a substrate having active regions; and

an interconnection system comprising;

a first patterned metal layer, comprising metal features, over the substrate;

a plurality of patterned metal layers, each patterned metal layer containing metal features, above the first patterned metal layer terminating with an uppermost patterned metal layer;

vias electrically connecting metal features of different patterned metal layers;

contact electrically connecting active regions to metal features of the first patterned metal layer;

air gaps, substantially continuous throughout the interconnection system, between the patterned metal layers, metal features, and vias; and

a conductive liner, comprising a material different from the metal features, directly on the metal features and vias, wherein the conductive liner substantially envelops all the metal features and vias.

2. The semiconductor device according to claim 1, further comprising a dielectric sealing layer between the substrate and first patterned metal layer.

3. The semiconductor device according to claim 2, further comprising dielectricc protective layers on the uppermost patterned metal layer.

4. The semiconductor device according to claim 3, wherein the conductive liner comprises a metal.

6. The semiconductor device according to claim 4, wherein the metal liner has a thickness of about 500 Å

to about 1,000 Å

.

12. The semiconductor device according to claim 1, wherein the conductive liner enhances the structural integrity of the semiconductor device and prevents a reduction in electromigration resistance.

13. The semiconductor device according to claim 2, wherein the dielectric sealing layer is a composite comprising a first layer and a second layer of a hydrophilic material on the first layer.

14. The semiconductor device according to claim 13, wherein the first layer comprises silicon nitride.

15. The semiconductor device according to claim 14, wherein the second layer comprise a fluoropolymer.

5. A semiconductor device comprising:

a substrate having active regions; and

an interconnection system comprising;

a first patterned metal layer, comprising metal features, over the substrate;

a plurality of patterned metal layers, each patterned metal layer containing metal features, above the first patterned metal layer terminating with an uppermost patterned metal layer;

vias electrically connecting metal features of different patterned metal layers;

contact electrically connecting active regions to metal features of the first patterned metal layer;

air gaps, substantially continuous throughout the interconnection system, between the patterned metal layers, metal features, and vias; and

a conductive liner, comprising a material different from the metal features, directly on the metal features and vias, wherein the conductive liner substantially envelops all the metal features and vias, and wherein the conductive liner comprises tungsten, molybdenum, osmium, iridium or an alloy thereof.

7. The semiconductor device according to claim 5, wherein the dielectric sealing layer comprises silicon nitride, or composite of a hydrophobic material on silicon nitride.

8. The semiconductor device according to claim 7, wherein the dielectric sealing layer has a thickness of about 500 Å

to about 1,000 Å

.

9. The semiconductor device according to claim 7, wherein the dielectric protective layers comprise a bottommost protective layer of an oxide.

10. The semiconductor device according to claim 9, wherein the bottommost protective oxide layer has a thickness of about 5,000 Å

to about 15,000 Å

.

11. The semiconductor device according to claim 5, wherein the conductive liner consists essentially of tungsten, molybdenum, osmium, iridium or an alloy thereof.

16. The semiconductor device according to claim 5, wherein the conductive liner comprises osmium, indium or an alloy thereof.

17. The method according to claim 16, wherein the patterned metal layer comprises aluminum, copper or an alloy thereof.

18. A method of manufacturing a semiconductor device, the method comprising:

forming a substrate with active regions;

forming an interconnection system comprising;

a first patterned metal layer comprising metal features over the substrate,

a plurality of patterned metal layers each of which containing metal features, above the first patterned metal layer terminating with an uppermost patterned metal layer;

vias electrically connecting metal features of different patterned metal layers;

contact electrically connecting active regions to metal features of the first patterned metal layer; and

an inter-layer dielectric between the patterned metal layers,

removing the inter-layer dielectric, and having air gaps substantially continuous throughout the interconnection system, between the patterned metal layers, metal features and vias; and

forming a conductive liner, comprising material different from that of the metal features, directly on the metal features and vias, wherein the conductive liner substantially envelopes all the metal features and vias.

19. The method according to claim 18, further comprising:

forming a dielectric sealing layer on the substrate; and

forming the first patterned metal layer on the dielectric sealing layer.

20. The method according to claim 19, further comprising forming electric protective layers on the uppermost patterned metal layer.

21. The method according to claim 20, comprising:

forming the inter-layer dielectrics by depositing layers of a;

lead-rich glass soluble in acetic acid;

benzocyclobutene resin;

or silica at a temperature less than about 400°

C.; and

removing the inter-layer dielectrics.

22. The method according to claim 20, comprising forming the conductive liner by selectively depositing a metal on the metal features and vias.

23. The method according to claim 20, wherein the dielectric sealing layer comprises a silicon nitride, or composite of a hydrophobic material on silicon nitride, and the dielectric protective layers comprise a bottommost protective layer of an oxide.

24. The method according to claim 22, comprising electroplating or electroless plating tungsten (W), molybdenum (Mo), osmium (Os), iridium (Ir) or an alloy thereof to form the conductive liner.

25. The method according to claim 22, comprising pulse electroplating the metal to form the conductive liner.

26. The method according to claim 25, comprising pulse electroplating the metal in a plurality of stages with non-electroplating periods of sufficient duration to permit diffusion of the plating metal to the surfaces of the metal features and vias.

27. The method according to claim 26, comprising pulse electroplating the metal with non-electroplating periods of about 10 to about 60 seconds.