PMOS low drop-out voltage regulator using non-inverting variable gain stage

• US 6,246,221 B1
• Filed: 09/20/2000
• Issued: 06/12/2001
• Est. Priority Date: 09/20/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Xi, Xiaoyu
• Primary Examiner(s): Riley, Shawn
• Application Number:
  US09/665,816
• Time in Patent Office: 265 Days
• Field of Search: 323/280, 323/316, 323/313, 323/274
• US Class Current: 323/280
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A high power supply ripple rejection (PSRR) internally compensated low drop-out voltage regulator using an output PMOS pass device. The voltage regulator uses a non-inversion variable gain amplifier stage to adjust its gain in response to a load current passing through the output PMOS device such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed above a unity gain frequency associated with the voltage regulator. The non-inversion variable gain amplifier is further operational to adjust its gain in response to a load current passing through the power PMOS device such that as the load current increases, the gain decreases, wherein the voltage regulator unity gain bandwidth associated with the loop formed by the compensation capacitor is kept substantially constant.

Claims

1. A modified Miller-compensated voltage regulator having a unity gain frequency, the voltage regulator comprising:

an input error amplifier stage comprising a differential amplifier having an output, a first input and a second input;

a non-inversion variable gain amplifier stage having an output, a first input in communication with the differential amplifier output, and a second input connected to a dc voltage referenced to ground;

a unity gain buffer amplifier stage having an output, a first input in communication with the non-inversion amplifier stage output and a second input coupled to the output of the unity gain buffer amplifier stage;

a power PMOS having a gate in communication with the unity gain buffer amplifier stage output, a source coupled to a supply voltage and a drain that is configured to provide a regulated output voltage; and

a compensating capacitor coupled at one end to the drain of the power PMOS and coupled at its other end to the output of the input error amplifier stage to provide a compensation loop having internal poles and a unity gain frequency associated therewith.

2. The modified Miller compensated voltage regulator according to claim 1 further comprising a filter capacitor coupled at one end to the drain of the power PMOS and coupled at its opposite end to ground.

3. The modified Miller compensated voltage regulator according to claim 1 further comprising a voltage divider coupled to the drain of the power PMOS and configured to provide a feedback voltage to the second input of the differential amplifier.

4. The modified Miller compensated voltage regulator according to claim 3 wherein the first input of the differential amplifier is coupled to a predetermined reference voltage.

5. The modified Miller compensated voltage regulator according to claim 1 wherein the non-inversion variable gain amplifier is operational to adjust its gain in response to a load current such that as the load current increases, the gain decreases, wherein the unity gain bandwidth associated with the loop formed by the compensating (Miller) capacitor is kept substantially constant.

6. The modified Miller compensated voltage regulator according to claim 1 wherein the non-inversion variable gain amplifier is operational to push the internal poles in the compensation loop itself formed by the compensating capacitor to frequencies above the unity gain frequency associated with the compensation loop.

7. The modified Miller compensated voltage regulator according to claim 1 wherein the non-inversion variable gain amplifier is operational to adjust its gain in response to a load current such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed away from the unity gain frequency associated with the voltage regulator.

8. A modified Miller compensated voltage regulator comprising:

a differential amplifier input stage having a first input, a second input, and an output;

a non-inversion variable gain amplifier stage having an output, a first input connected to a reference voltage, and a second input coupled to the output of the differential amplifier input stage;

a PMOS output transistor having a source, drain and gate;

a unity gain buffer coupling the non-inversion variable gain amplifier stage to the gate of the PMOS output transistor; and

a feedback capacitor coupled at a first end to the PMOS output transistor drain, and coupled at a second end to the non-inversion variable gain amplifier stage second input to form a compensation loop;

wherein the non-inversion variable gain amplifier stage, the unity gain buffer, the PMOS output transistor, and the feedback capacitor are responsive to a changing load current to control a unity gain bandwidth associated with the compensation loop.

9. The modified Miller compensated voltage regulator according to claim 8 wherein the feedback capacitor is referenced at both ends to a common ground associated with the voltage regulator.

10. The modified Miller compensated voltage regulator according to claim 8 further comprising a filter capacitor (CFILT) coupled at one end to the drain of the power PMOS and coupled at its opposite end to ground.

11. The modified Miller compensated voltage regulator according to claim 10 wherein the unity gain bandwidth associated with the compensation loop is defined by the equation $f_{\mathrm{bwMILLER}}=\frac{A_2·}{}$

GmMPO2

π

·

CFILT,

where A₂ is a gain associated with the non-inversion variable gain amplifier and G_mMPO is a transconductance associated with the power PMOS.

12. A modified Miller compensated voltage regulator comprising:

an input amplifier stage configured to receive an input reference voltage and further configured to receive a feedback current via a nested Miller compensation capacitor associated with the voltage regulator to generate a displacement current to provide an effective Miller multiplied compensating capacitance;

a non-inversion variable gain amplifier stage having an output pole associated therewith, the non-inversion variable gain amplifier stage configured to receive the feedback displacement current associated with the nested Miller compensation capacitor such that the pole associated with the output of the non-inversion variable gain amplifier stage is pushed out to a frequency above a Unity Gain Frequency associated with the compensation loop and further configured to generate an amplified displacement current signal therefrom; and

an output amplifier stage having a pole associated therewith, the output amplifier stage configured to receive the amplified displacement current signal such that the pole associated with the output amplifier stage is pushed out to a frequency above the Unity Gain Frequency of the compensation loop thereby rendering the voltage regulator output stage capable of generating a stable regulated output voltage at frequencies in the vicinity of the control loop bandwidth associated with the voltage regulator.

13. A modified Miller compensated voltage regulator comprising:

means for generating a feedback current;

means for generating a displacement current from the feedback current;

means for amplifying the displacement current such that non-dominant poles associated with the voltage regulator are pushed to frequencies outside the control loop bandwidth of the voltage regulator; and

means for generating output voltage signals having substantially maximized power supply ripple rejection characteristics inside the control loop bandwidth.

14. The modified Miller compensated voltage regulator according to claim 13 wherein the means for generating a feedback current comprises a power PMOS device.

15. The modified Miller compensated voltage regulator according to claim 14 wherein the means for generating output voltage signals having substantially maximized power supply ripple rejection characteristics inside the control loop bandwidth comprises a unity gain buffer configured to receive the displacement current and drive the power PMOS device therefrom.

16. The modified Miller compensated voltage regulator according to claim 14 wherein the means for generating output voltage signals having substantially maximized power supply ripple rejection characteristics inside the control loop bandwidth comprises a source follower configured to receive the displacement current and drive the power PMOS device therefrom.

17. The modified Miller compensated voltage regulator according to claim 14 wherein the means for generating a feedback current further comprises a nested Miller compensation capacitor.

18. The modified Miller compensated voltage regulator according to claim 17 wherein the nested Miller compensation capacitor is configured such that each capacitor node is referenced to a common ground associated with the voltage regulator.

19. The modified Miller compensated voltage regulator according to claim 13 wherein the means for generating a displacement current comprises a voltage divider.

20. The modified Miller compensated voltage regulator according to claim 13 wherein the means for amplifying the displacement current such that non-dominant poles associated with the voltage regulator are pushed to frequencies outside the control loop bandwidth of the voltage regulator comprises a non-inversion variable gain amplifier.

21. A modified Miller compensated voltage regulator comprising:

a supply voltage node;

an output voltage node;

a ground;

an output power PMOS device having a source connected to the supply voltage node, a drain connected to the output voltage node, and a gate;

a common source PMOS device having a source connected to the supply voltage node, a gate connected to the gate of the power PMOS device, and a drain;

a unity gain buffer having a bias input connected to the drain of the common source PMOS device, an output connected to the gate of the power PMOS device, an inverting input connected to the buffer output, and a non-inverting input;

a non-inversion variable gain amplifier having an output connected to the unity gain buffer non-inverting input, a reference voltage input connected to a ground reference voltage, and a non-inverting input;

a differential amplifier having a bias input connected to the supply voltage node, an output connected to the non-inverting input of the non-inversion variable gain amplifier, an inverting input connected to a reference voltage, and a non-inverting input;

a voltage divider network having a first node connected to the power PMOS drain, a second node connected to ground, and a third node connected to the differential amplifier non-inverting input to provide a feedback voltage; and

a compensation capacitor connected at one end to the power PMOS device drain and connected at an opposite end to differential amplifier output.

22. The modified Miller compensated voltage regulator according to claim 21 further comprising a filter capacitor coupled at one end to the drain of the power PMOS device and connected at its opposite end to ground.

23. The modified Miller compensated voltage regulator according to claim 22 wherein the non-inversion variable gain amplifier, unity gain buffer, the power PMOS device, common source PMOS device, voltage divider network, filter capacitor, and compensation capacitor are responsive to a changing load current to control a unity gain bandwidth associated with the compensation loop.

24. The modified Miller compensated voltage regulator according to claim 21 wherein the non-inversion variable gain amplifier is operational to adjust its gain in response to a load current passing through the power PMOS device such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed above a unity gain frequency associated with the voltage regulator.

25. The modified Miller compensated voltage regulator according to claim 21 wherein the non-inversion variable gain amplifier is operational to adjust its gain in response to a load current passing through the power PMOS device such that as the load current increases, the gain decreases, wherein the voltage regulator unity gain bandwidth associated with a loop formed by the compensation capacitor is dept substantially constant.