Realizing analog-to-digital converter on a digital programmable integrated circuit

• US 6,246,258 B1
• Filed: 06/21/1999
• Issued: 06/12/2001
• Est. Priority Date: 06/21/1999
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lesea, Austin H.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/337,855
• Time in Patent Office: 722 Days
• Field of Search: 326/37-41, 341/126, 341/141, 341/155
• US Class Current: 326/39
• CPC Class Codes: H03M 1/004 Reconfigurable analogue/digital or digital/analogue converters H03M1/02 takes precedence
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter

Abstract

An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC. In some embodiments, an interface cell has a pad that is usable for receiving a digital signal or for receiving an analog signal. The interface cell includes special dedicated analog circuitry that has a differential input lead that is programmably couplable to the pad.

Claims

1. A method, comprising:

using a comparator of a first interface cell to receive a digital signal onto a programmable integrated circuit, the programmable integrated circuit comprising the first interface cell, a second interface cell and a plurality of configurable logic blocks; and

using a comparator of the second interface cell to receive an analog signal onto the programmable integrated circuit, and using the comparator of the second interface cell to generate a multibit digital signal indicative of a magnitude of the analog signal, the first interface cell and the second interface cell being substantially structurally identical, the comparator of the first interface cell corresponding to and being substantially structurally identical to the comparator of the second interface cell.

2. The method of claim 1, wherein the first comparator compares the digital signal to a reference voltage, and wherein the second comparator compares the analog signal to a feedback signal, the second comparator being part of an analog-to-digital converter, the feedback signal being a feedback signal of the analog-to-digital converter.

3. The method of claim 1, wherein the programmable integrated circuit is a field programmable gate array and comprises a common conductor,

wherein the first interface cell comprises a first pad and a second pad, a first differential input lead of the comparator of the first interface cell being coupled to the first pad of the first interface cell, a second differential input lead of the comparator of the first interface cell being prograimably couplable to the second pad of the first interface cell or to the common conductor, the second differential input lead of the comparator of the first interface cell being coupled to the common conductor, and

wherein the second interface cell comprises a first pad and a second pad, a first differential input lead of the comparator of the second interface cell being coupled to the first pad of the second interface cell, a second differential input lead of the comparator of the second interface cell being programmably couplable to the second pad of the second interface cell or to the common conductor, the second differential input lead of the second interface cell being coupled to the second pad of the second interface cell.

4. The method of claim 1, wherein the first comparator compares the digital signal to a reference voltage, and wherein the second comparator is one of a plurality of comparators of a flash analog-to-digital converter.

5. The method of claim 1, wherein the first comparator compares the digital signal to a reference voltage, and wherein the second comparator is a part of a successive approximation analog-to-digital converter.

6. The method of claim 1, wherein the second interface cell comprises a first pad and a second pad, a first differential input lead of the comparator of the second interface cell being coupled to the first pad of the second interface cell, a second differential input lead of the comparator of the second interface cell being coupled to the second pad of the second interface cell.

7. The method of claim 4, wherein the programmable integrated circuit further comprises a third interface cell, the third interface cell having a pad, and wherein the comparator of the second interface cell receives the analog signal through the pad of the third interface cell.

8. The method of claim 4, wherein the programmable integrated circuit comprises a plurality of interface cells of the analog-to-digital converter, the second interface cell being one of the plurality of interface cells of the analog-to-digital converter, the plurality of interface cells of the analog-to-digital converter extending in a column parallel to an edge of the programmable integrated circuit, each of the plurality of comparators of the analog-to-digital converter being part of a respective one of the plurality of interface cells of the analog-to-digital converter, each of the plurality of comparators of the analog-to-digital converter having a differential input lead, the programmable integrated circuit further comprising a common conductor that extends in a direction substantially parallel to the edge of the programmable integrated circuit, the common conductor being coupled to the differential input lead of each of the plurality of comparators of the analog-to-digital converter, the analog signal being present on the common conductor.

9. The method of claim 8, wherein each of the plurality of interface cells of the analog-to-digital converter comprises a pad, the method further comprising:

coupling the pad of each of the plurality of interface cells of the analog-to-digital converter to a respective one of a plurality of taps of a multi-tap resistor string.

10. The method of claim 9, wherein the programmable integrated circuit further comprises another interface cell, the analog signal being present on a pad of this other interface cell, the pad of this other interface cell being coupled to the common conductor such that the analog signal is present on the common conductor.

11. The method of claim 4, wherein the analog-to-digital converter comprises an encoder, the method further comprising:

configuring the plurality of configurable logic blocks of the programmable integrated circuit to realize the encoder.

12. A programmable integrated circuit, comprising:

a plurality of configurable logic blocks;

a common conductor; and

a plurality of interface cells, each of the interface cells comprising;

a first pad;

a second pad;

a comparator having a first differential input lead, a second differential input lead, and an output lead;

first coupling means for coupling the first differential input lead to the first pad;

second coupling means for programmably coupling the second differential input lead to one of the second pad and the common conductor; and

a digital logic element having an input lead, the input lead being couplable to the output lead of the comparator.

13. The programmable integrated circuit of claim 12, wherein the first coupling means does not amplify a signal that passes from the first pad to the first differential input lead.

14. The programmable integrated circuit of claim 12, wherein the first coupling means comprises:

a memory cell; and

a transistor, the transistor being conductive and coupling the first pad to the first differential input lead when the memory cell contains first data, the transistor being nonconductive when the memory cell contains second data.

15. The programmable integrated circuit of claim 12, wherein the second coupling means comprises:

a memory cell; and

a transistor, the transistor being conductive and coupling the second pad to the second differential input lead when the memory cell contains first data, the transistor being nonconductive when the memory cell contains second data.

16. The programmable integrated circuit of claim 12, wherein the second coupling means comprises:

a memory cell; and

a transistor, the transistor being conductive and coupling the common conductor to the second differential input lead when the memory cell contains first data, the transistor being nonconductive when the memory cell contains second data.

17. The programmable integrated circuit of claim 12, wherein the second coupling means of each interface cell is programmable to form a connection from the second pad of the interface cell to the second differential input lead of the comparator of the interface cell, the connection having an impedance of less than one hundred ohms into ten picofarads, the connection not extending into any other interface cell.

18. The programmable integrated circuit of claim 12, wherein the comparators of a first plurality of the interface cells A are part of a flash analog-to-digital converter, the flash analog-to-digital converter also comprising an encoder, a plurality of the configurable logic blocks being configured to realize the encoder, the encoder having a plurality of input leads, the output lead of each respective comparator of the interface cells A being coupled to a corresponding respective one of the input leads of the encoder.

19. The programmable integrated circuit of claim 18, wherein an analog input signal is driven onto the common conductor, the second differential input lead of each comparator of the interface cells A being coupled to the common conductor, the encoder having a plurality of output leads, a digital value being present on the plurality of output leads of the encoder, the digital value being indicative of a magnitude of the analog input signal.

20. The programmable integrated circuit of claim 19, further comprising:

a resistor string, a second plurality of interface cells B also being part of the flash analog-to-digital converter, one of the interface cells B coupling a first voltage onto one end of the resistor string, another of the interface cells B coupling a second voltage onto another end of the resistor string.

21. The programmable integrated circuit of claim 18, wherein an interface cell C of the programmable integrated circuit is part of the flash analog-to-digital converter, a pad of the interface cell C being driven with an analog input voltage, the pad of the interface cell C being coupled to the common conductor, the encoder having a plurality of output leads, a digital value being present on the plurality of output leads of the encoder, the digital value being indicative of a magnitude of the analog input signal.

22. The programmable integrated circuit of claim 18, wherein an analog input signal is driven onto the second pad of each of the interface cells A, the second differential input lead of each comparator of the interface cells A being coupled to its corresponding second pad.

23. The programmable integrated circuit of claim 12, wherein the first coupling means is not a programmable connection.

24. The programmable integrated circuit of claim 12, wherein the first coupling means includes an input protection transistor, the first differential input lead being coupled to the first pad through the input protection transistor.

25. The programmable integrated circuit of claim 12, wherein the first coupling means is a programmable connection.

26. A field programmable gate array comprising a plurality of configurable logic blocks and a plurality of interface cells, each of the interface cells comprising:

a pad;

a first comparator having a differential input lead and an output lead;

a node internal to the interface cell;

means for (i) supplying a digital signal on the pad to the node, or (ii) supplying an analog signal on the pad to the differential input lead of the first comparator such that a digital signal on the output lead of the first comparator is supplied to the node.

27. The field programmable gate array of claim 26, wherein the means comprises a second comparator and a multiplexer, a first differential input lead of the second comparator being coupled to the pad, a second differential input lead of the second comparator being coupled to a reference voltage conductor, an output lead of the second comparator being coupled to a first input lead of the multiplexer, a second input lead of the multiplexer being coupled to the output lead of the first comparator, an output lead of the multiplexer being coupled to the node.

28. The field programmable gate array of claim 26,

wherein a digital signal is present on the pad of a first interface cell of the interface cells, the digital signal being supplied to the node of the first interface cell by the means, and

wherein an analog signal is present on the pad of a second interface cell of the interface cells, the analog signal being supplied to the differential input lead of the first comparator of the second interface cell, a digital signal on the output lead of the first comparator being supplied by the means onto the node of the second interface cell, the first interface cell and the second interface cell being substantially structurally identical.

29. The field programmable gate array of claim 28, wherein the first comparator of the second interface cell is a part of a multi-bit analog-to-digital converter.

30. The field programmable gate array of claim 26, wherein each interface cell further comprises:

a second pad, the pad being programmably couplable to a second differential input lead of the first comparator.

31. The field programmable gate array of claim 26 further comprising a common conductor, wherein each of the interface cells further comprises:

means for coupling the differential input lead of the first comparator to the common conductor.

32. The field programmable gate array of claim 26 further comprising a multi-tap resistor string, the multi-tap resistor string being a part of the field programmable gate array, wherein each of the interface cells further comprises:

means for coupling the differential input lead of the first comparator to a tap of the multi-tap resistor string, wherein the plurality of interface cells forms part of an analog-to-digital converter.

33. In a programmable integrated circuit comprising an array of configurable logic blocks and first and second configurable interface cells, the first and second configurable interface cells being substantially structurally identical to each other, each of the first and second configurable interface cells including a comparator, a method comprising:

applying a digital signal to the comparator of the first configurable interface cell;

applying an analog signal to the comparator of the second configurable interface cell; and

using the comparator of the second configurable interface cell to generate part of a multi-bit signal indicating the magnitude of the analog signal.

34. A programmable integrated circuit, comprising:

a first bank of configurable interface cells disposed along an edge of the programmable integrated circuit, each interface cell of the first bank comprising a comparator and a pad, the comparator having a first differential input lead and a second differential input lead, the first differential input lead being coupled to the pad;

a first conductor that extends in a direction substantially parallel to the edge of the programmable integrated circuit, the first conductor being coupled to the second differential input lead of the comparator of each of the comparators of the first bank of configurable interface cells;

a second bank of configurable interface cells disposed along the edge of the programmable integrated circuit, each interface cell of the second bank comprising a comparator and a pad, the comparator having a first differential input lead and a second differential input lead, the first differential input lead being coupled to the pad; and

a second conductor that extends in a direction substantially parallel to the edge of the programmable integrated circuit, the second conductor being coupled to the second differential input lead of the comparator of each of the comparators of the second bank of configurable interface cells;

wherein a reference voltage is present on the first conductor, and wherein a digital input signal is received on the pad of the comparator of one of the configurable interface cells of the first bank, and

wherein an analog input signal is present on the second conductor, and wherein the configurable interface cells of the second bank form a part of an analog-to-digital converter, the analog-to-digital converter converting the analog input signal into a multibit digital value, wherein each of the configurable interface cells of the first bank and each of the configurable interface cells of the second bank has a substantially identical structure.

35. A programmable integrated circuit, comprising:

a plurality of configurable logic blocks;

a common conductor, a reference voltage being present on the common conductor;

a first interface cell comprising a comparator and a pad, the comparator of the first interface cell comparing a digital signal on the pad to the reference voltage on the common conductor; and

a second interface cell comprising a comparator and a pad, the comparator of the second interface cell being part of an analog-to-digital converter, the analog-to-digital converter outputting a multibit digital value indicative of a magnitude of an analog signal present on the pad of the second interface cell, the first interface cell and the second interface cell being substantially structurally identical.

36. The programmable integrated circuit of claim 35, wherein the first interface cell further comprises:

a second pad; and

means for programmably coupling a differential input lead of the comparator of the first interface cell to either the common conductor or to the second pad of the first interface cell,

and wherein the second interface cell further comprises;

a second pad; and

means for programmably coupling a differential input lead of the comparator of the second interface cell to either the common conductor or to the second pad of the second interface cell.