Output buffer for a low voltage differential signaling receiver

• US 6,246,262 B1
• Filed: 02/24/2000
• Issued: 06/12/2001
• Est. Priority Date: 02/24/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Morgan, Mark W., Carvajal, Fernando D.
• Primary Examiner(s): Wamsley, Patrick
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/512,995
• Time in Patent Office: 474 Days
• Field of Search: 326/17, 326/27, 326/57-58, 326/112, 326/119, 326/121, 326/80, 326/81, 326/83, 326/86, 326/87, 327/534, 327/544
• US Class Current: 326/81
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits

Abstract

A three-state CMOS output buffer (200), having protective circuitry and an output node (OUT) connected to a bus, prevents damage to a connected integrated circuit when the bus voltage exceeds a power supply reference voltage (V_CC). A final output stage of the output buffer (200) includes a first pull-up transistor (QP200), a clamping transistor (QN202), and a pull-down transistor (QN204). A half-pass circuit (QN200) blocks the output voltage from propagating through the final output stage to damage the output buffer (200) when the output voltage applied to the output node (OUT) exceeds the supply voltage. The protective circuitry uses a clamping circuit (210), a switching circuit (212) and a backgate bias circuit (206) to prevent a leakage path between the output node (OUT) and the power supply reference (V_CC) through the source/bulk junction of biased transistors in the output buffer (200). The clamping circuit (210) turns the pull-up transistor (QP200) fully off when the output buffer (200) is enabled and an input signal (V_IN) is high and when the output buffer (200) is disabled. When the output buffer (200) is disabled, the switching circuit (212) turns the clamping circuit (210) off prior to turning the half pass circuit (QN200) and the pull-up transistor (QP200) off. The backgate bias circuit (206) provides a bias voltage equivalent to the power supply reference voltage (V_CC), as long as the bus voltage is not higher than the power supply reference voltage (V_CC), and bias equivalent to the bus voltage, when the bus voltage exceeds the power supply reference voltage (V_CC). Thus, the protective circuitry provides protection without a glitch of bus voltage propagating through the final output stage.

Claims

1. A three-state CMOS output buffer having a first power supply reference voltage, second power supply reference voltage, and an output coupled to a bus, the bus having a voltage, the three-state CMOS output buffer comprising:

a final output stage comprising a pull-up transistor, a clamping transistor, and a pull-down transistor connected respectively in series between a power supply rail and ground and having an common output node between the clamping transistor and the pull-up transistor;

a half-pass circuit coupled to the final output stage, the half-pass circuit blocks the bus voltage from propagating through to damage the output buffer when the output voltage applied to the output node exceeds the first power supply reference voltage;

a control circuit coupled to the half-pass circuit, the control circuit supplied with an input data signal, an enable/disable signal and a complemented enable/disable signal for activating and deactivating the final output stage;

an invertor coupled to the control circuit;

a clamping circuit coupled to the invertor and the final output stage to turn the pull-up transistor fully off when the output buffer is enabled and the input data signal is low and when the output buffer is disabled;

a switching circuit coupled to the half-pass circuit, the clamping circuit and the pull-up transistor, such that when the output buffer is disabled, the switching circuit turns the clamping circuit off prior to turning the half pass circuit and the pull-up transistor off for guarding the output buffer and the first power supply against voltages applied to the output node of the buffer that exceed the first power supply reference voltage; and

a backgate bias circuit coupled to the backgate of the pull-up transistor, the clamping circuit, and the switching circuit, the backgate bias circuit supplies the first power supply reference voltage as long as the output node is not higher than a supply voltage, the backgate bias circuit supplies the output voltage when the output node is higher than the first power supply reference voltage.

2. The three-state CMOS output buffer of claim 1, wherein the half-pass circuit includes a first transistor, the first transistor connected between the control circuit and the pull-up transistor, the first transistor having a gate coupled to the first power supply reference voltage and a backgate coupled to ground.

3. The three-state CMOS output buffer of claim 1, wherein the control circuit comprises:

a first logic gate supplied with an input data signal and an enable/disable signal, the first logic gate driving the pull-up transistor; and

a second logic gate supplied with an input data signal and the complement of the an enable/disable signal, the first and second logic gates responsive to the enable/disable signal for activating a three-state mode in which the pull-up transistor and the pull-down transistor are both deactivated.

4. The three-state CMOS output buffer of claim 3, wherein the first logic gate includes an output node and at least two input nodes and comprises a NAND gate having a first transistor, a second transistor, a third transistor and a fourth transistor, the first transistor and the second transistor coupled between the voltage supply and the output node of the first logic gate, the third transistor coupled between the fourth transistor and the coupled first and second transistors, the first and third transistors coupled to a first one of the two input nodes, the second and fourth transistors coupled to the second one of the two input nodes.

5. The three-state CMOS output buffer of claim 3, wherein the second logic gate including a output node and at least two input nodes, the first input node coupled to the input data signal, the second input node coupled to the enable/disable signal, comprises a NOR gate having a first transistor, a second transistor, a third transistor and a fourth transistor, the first transistor coupled between the voltage supply and the second transistor, the third transistor and the fourth transistor coupled between the second transistor and ground, the second and third transistors coupled to the first input node, the first and fourth transistors coupled to the second input node.

6. The three-state CMOS output buffer of claim 1, wherein the clamping circuit comprises a first transistor and an second transistor coupled in series between the voltage supply and a gate of the pull-up transistor, the first transistor and the second transistor having a backgate coupled to the backgate bias circuit.

7. The three-state CMOS output buffer of claim 1, wherein the switching circuit comprises:

a first transistor coupled between the clamping circuit and the output node, the first transistor having a backgate coupled to the backgate bias circuit and a gate;

a second transistor having a drain coupled to the source of the first transistor, a gate coupled to the first power supply reference voltage, and a directly coupled backgate and source, the directly coupled backgate and source couple to ground;

a third transistor having a gate, a drain coupled to the gate of the first transistor and a directly coupled backgate and source, the directly coupled backgate and source couple to the first power supply reference voltage;

a fourth transistor having a directly coupled gate and drain, a backgate coupled to the first power supply reference voltage, a source coupled to the drain of the third transistor; and

a fifth transistor having a drain coupled to the gate of the fourth transistor, a gate coupled to the first power supply reference voltage and a directly coupled backgate and source coupled to ground.

8. The three-state CMOS output buffer of claim 1, wherein the backgate bias circuit comprises:

a first transistor having a drain coupled to the complemented enable/disable signal, a backgate coupled to ground, a gate and a source;

a second transistor having a gate coupled to the source of the first transistor, a source coupled to the gate of the first transistor, and a directly coupled backgate and drain to form a bias output node; and

a third transistor having a source coupled to the gate of the second transistor, a gate coupled to the enable/disable signal, and a directly coupled backgate and drain coupled to the bias output node.