Display driving circuit for displaying character on display panel

• US 6,246,388 B1
• Filed: 05/10/1999
• Issued: 06/12/2001
• Est. Priority Date: 05/14/1998
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Motegi, Syuji, Arai, Hiroyuki, Tokunaga, Tetsuya
• Primary Examiner(s): CHANG, KENT WU
• Application Number:
  US09/309,035
• Time in Patent Office: 764 Days
• Field of Search: 345/197, 345/192, 345/196, 345/508, 345/98, 345/99, 345/100, 345/141
• US Class Current: 345/98
• CPC Class Codes: G09G 2310/0278 Details of driving circuits arranged to drive both scan and data electrodes
• CPC Class Codes: G09G 3/04 for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 5/222 Control of the character-code memory

Abstract

For changing the content of a display RAM (38) or an accessory RAM (39), various data SDI, such as an instruction code, address data, display data, is initially transferred to a shift register (11). Then, the display data in the shift register (11) is latched by a latch circuit (62). A write operation is carried out during a period from the completion of a shift operation by the shift register (11) using various data SDI in connection with the current display to the completion of a shift operation using various data SDI in connection with the next display, i.e., a period with an operation enable signal CE remaining at an L or H level. As a result, time allowance for writing is ensured, which contributes to reduction of software processing load by an external device.

Claims

1. A display driving circuit for displaying a predetermined character on a display panel, comprising:

a shift register for serially receiving display data during a period when an operation enable signal remains at one logical level;

a latch circuit for latching the display data from said shift register in synchronism with a timing at which the operation enable signal changes from the one logical level to another logical level;

a display memory for being written the display data from said latch circuit; and

a panel driving circuit for displaying on the display panel a character corresponding to the display data read from said display memory.

2. A circuit according to claim 1, wherein said shift register receives address data indicative of a write start address for the display data as well as the display data.

3. A circuit according to claim 2, further comprising a write address counter for receiving the address data indicative of a write start address supplied to said shift register, and for sequentially changing the address data for designation of a write address in said display memory.

4. A circuit according to claim 3, wherein said shift register receives instruction data including a write instruction for the display data as well as the display data and the address data, and said circuit further comprises an instruction decoder for decoding the instruction data to generate a signal including a write enable signal.

5. A circuit according to claim 4, wherein the display data, the address data, and the instruction data are input into said shift register when starting writing of the display data into said display memory, the display data is sequentially input into said shift register during the writing, and the display data and instruction data are input into said shift register when ending the writing.

6. A circuit according to claim 1, wherein input of the next display data into said shift register is carried out in parallel to writing of the current display data from said latch circuit to said display memory.