Electrical fault detection system

• US 6,246,556 B1
• Filed: 02/19/1998
• Issued: 06/12/2001
• Est. Priority Date: 03/13/1995
• Status: Expired due to Term

• Current Assignee: Square D Company (Schneider Electric SE)
• Original Assignee: Square D Company (Schneider Electric SE)
• Inventors: Haun, Andrew A., Coats, Alan G., Scott, Gary W., Dvorak, Robert F., Wong, Kon B.
• Primary Examiner(s): Leja, Ronald W.
• Application Number:
  US09/026,193
• Time in Patent Office: 1,209 Days
• Field of Search: 361/42-50, 361/93.6
• US Class Current: 361/42
• CPC Class Codes: H01H 2083/201 the other abnormal electrical condition being an arc fault
• CPC Class Codes: H01H 71/125 characterised by sensing elements, e.g. current transformers for differential protection H01H83/144
• CPC Class Codes: H02H 1/0015 Using arc detectors
• CPC Class Codes: H02H 1/06 Arrangements for supplying operative power power supply arrangements in general G05F, H02M
• CPC Class Codes: H02H 3/105 responsive to excess current and fault current to earth
• CPC Class Codes: H02H 3/44 responsive to the rate of change of electrical quantities

Abstract

An electrical fault detector system detects electrical faults in an electrical distribution system by monitoring one or more conductors and producing an input signal representing one or more electrical signal conditions in the circuit to be monitored. This input signal is processed to develop a first signal representing the electrical current flow through the monitored circuit and a second signal representing signal components in a selected frequency range typical of arcing faults, and which exceed a predetermined threshold. The system also detects ground faults in the circuit being monitored.

Claims

1. An integrated circuit for use in a processor-controlled device connected to at least one electrical power line so that the combination of the integrated circuit and the processor-controlled device can detect faults in the power line, said integrated circuit comprising:

a first input for receiving an alternating signal from an arcing-fault sensor coupled to said power line;

at least one band pass filter connected to said first input for passing those components of said alternating signal within a prescribed frequency band;

a threshold detector receiving the components of said alternating signal passed by said filter for comparing those signal components with a predetermined threshold and producing an output signal when the predetermined threshold is exceeded;

a pulse generator receiving the output signal from the threshold detector and producing a corresponding output pulse;

a first output receiving the output pulses from the pulse generator for coupling those pulses to a processor;

an integrator connected to said first input for integrating said alternating signal and producing a signal representing the resulting integral;

an absolute value circuit receiving the integral signal from said integrator and producing an output signal representing the absolute value of that integral;

a second output receiving the absolute-value integral signal for coupling that signal to the processor;

a second input for receiving a signal from a ground-fault sensor coupled to said power line;

an amplifier connected to said second input for amplifying the ground-fault signal from the ground-fault sensor;

an absolute value circuit receiving the amplified ground-fault signal and producing an output signal representing the absolute value of the amplified ground-fault signal; and

a third output receiving the absolute-value ground-fault signal for coupling that signal to the processor.

3. The integrated circuit of claim 1, which includes a fourth input for receiving a test signal, an amplifier for adjusting the amplitude of said test signal, and a fourth output receiving the amplifier output for coupling the test signal to said arcing-fault sensor.

4. The integrated circuit of claim 1 which includes at least one power-line input for receiving the power line signal, signal conditioning means for adjusting at least the amplitude of the power line signal, and a power-line output receiving the adjusted power line signal for coupling that signal to the processor.

5. The integrated circuit of claim 1 which includes a watch-dog circuit for receiving a watch-dog signal output from the processor, determining from said watch-dog signal whether the processor is active, and producing a trip signal if it is determined that the processor is not active.

2. The integrated circuit of claim which includes:

a second band pass filter connected to said first input for passing those components of said alternating signal within a second prescribed frequency band;

a second threshold detector receiving the components of said alternating signal passed by said second filter for comparing those signal components with a second predetermined threshold and producing an output signal when the second predetermined threshold is exceeded;

a second pulse generator receiving the output signal from the second threshold detector and producing a corresponding output pulse;

logic means receiving said output pulses from both said pulse generators and passing said pulses when output pulses from both pulse generators occur at substantially the same time, and

said first output receiving the output pulses from said logic means for coupling those pulses to the processor.

6. An integrated circuit for use in a processor-controlled device connected to at least one electrical power line so that the combination of the integrated circuit and the processor-controlled device can detect faults in the power line, said integrated circuit comprising:

a first input for receiving and alternating signal from an arcing-fault sensor coupled to said power line;

a first band pass filter connected to said first input for passing those components of said alternating signal within a first prescribed frequency band;

a first threshold detector receiving the components of the alternating signal passed by said first filter for comparing those signal components with a first predetermined threshold and producing an output signal when the first predetermined threshold is exceeded;

a first pulse generator receiving the output signal from the first threshold detector and producing a corresponding output pulse;

a second band pass filter connected to said first input for passing those components of said alternating signal within a second prescribed frequency band;

a second threshold detector receiving the components of said the alternating signal passed by said second filter for comparing those signal components with a second predetermined threshold and producing an output signal when the second predetermined threshold is exceeded;

a second pulse generator receiving the output signal from the second threshold detector and producing a corresponding output pulse;

logic means receiving said output pulses from both said pulse generators and passing said pulses when output pulses from both pulse generators occur at substantially the same time;

a first output receiving the output pulses from said logic means for coupling those pulses to a processor;

an integrator connected to said first input for integrating said alternating signal and producing a signal representing the resulting integral;

an absolute value circuit receiving the integral signal from said integrator and producing an output signal representing the absolute value of that integral;

a second output receiving the absolute-value integral signal for coupling that signal to the processor;

a second input for receiving a signal from a ground-fault sensor coupled to said power line;

an amplifier connected to said second input for amplifying the ground-fault signal from the ground-fault sensor;

an absolute value circuit receiving the amplified ground-fault signal and producing an output signal representing the absolute value of the amplified ground-fault signal; and

a third output receiving the absolute-value ground-fault signal for coupling that signal to the processor;

a fourth input for receiving a test signal, an amplifier for adjusting the amplitude of said test signal, and a fourth output receiving the amplifier output for coupling the test signal to said arcing-fault sensor;

at least one power-line input for receiving the power line signal, signal conditioning means for adjusting at least the amplitude of the power line signal, and a power-line output receiving the adjusted power line signal for coupling that signal to the processor, and

a watch-dog circuit for receiving a watch-dog signal output from the processor, determining from said watch-dog signal whether the processor is active, and producing a trip signal if it is determined that the processor is not active.

7. A circuit for use in a processor-controlled device connected to at least one electrical power line so that the combination of the circuit and the processor-controlled device can detect faults in the power line, said circuit comprising:

a first input for receiving an alternating signal from an arcing-fault sensor coupled to said power line;

at least one band pass filter connected to said first input for passing those components of said alternating signal within a prescribed frequency band;

a threshold detector receiving the components of said alternating signal passed by said filter for comparing those signal components with a predetermined threshold and producing an output signal when the predetermined threshold is exceeded;

a pulse generator receiving the output signal from the threshold detector and producing a corresponding output pulse;

a first output receiving the output pulses from the pulse generator for coupling those pulses to a processor;

an integrator connected to said first input for integrating said alternating signal and producing a signal representing the resulting integral;

an absolute value circuit receiving the integral signal from said integrator and producing an output signal representing the absolute value of that integral; and

a second output receiving the absolute-value integral signal for coupling that signal to the processor.

8. The circuit of claim 7 which includes:

a second input for receiving a signal from a ground-fault sensor coupled to said power line;

an amplifier connected to said second input for amplifying the ground-fault signal from the ground-fault sensor;

an absolute value circuit receiving the amplified ground-fault signal and producing an output signal representing the absolute value of the amplified ground-fault signal; and

a third output receiving the absolute-value ground-fault signal for coupling that signal to the processor.

9. The circuit of claim 7 which includes:

a second band pass filter connected to said first input for passing those components of said alternating signal within a second prescribed frequency band;

a second threshold detector receiving the components of said alternating signal passed by said second filter for comparing those signal components with a second predetermined threshold and producing an output signal when the second predetermined threshold is exceeded;

a second pulse generator receiving the output signal from the second threshold detector and producing a corresponding output pulse;

logic means receiving said output pulses from both said pulse generators and passing said pulses when output pulses from both pulse generators occur at substantially the same time, and

said first output receiving the output pulses from said logic means for coupling those pulses to the processor.

10. The circuit of claim 7 which includes a fourth input for receiving a test signal, an amplifier for adjusting the amplitude of said test signal, and a fourth output receiving the amplifier output for coupling the test signal to said arcing-fault sensor.

11. The circuit of claim 7 which includes at least one power-line input for receiving the power line signal, signal conditioning means for adjusting at least the amplitude of the power line signal, and a power-line output receiving the adjusted power line signal for coupling that signal to the processor.

12. The circuit of claim 7 which includes a watch-dog circuit for receiving a watch-dog signal output from the processor, determining from said watch-dog signal whether the processor is active, and producing a trip signal if it is determined that the processor is not active.

13. A circuit for use in a processor-controlled device connected to at least one electrical power line so that the combination of the circuit and the processor-controlled device can detect faults in the power line, said circuit comprising:

a first input for receiving an alternating signal from an arcing-fault sensor coupled to said power line;

a first band pass filter connected to said first input for passing those components of said alternating signal within a first prescribed frequency band;

a first threshold detector receiving the components of the alternating signal passed by said first filter for comparing those signal components with a first predetermined threshold and producing an output signal when the first predetermined threshold is exceeded;

a first pulse generator receiving the output signal from the first threshold detector and producing a corresponding output pulse;

a second band pass filter connected to said first input for passing those components of said alternating signal within a second prescribed frequency band;

a second threshold detector receiving the components of said alternating signal passed by said second filter for comparing those signal components with a second predetermined threshold and producing an output signal when the second predetermined threshold is exceeded;

a second pulse generator receiving the output signal from the second threshold detector and producing a corresponding output pulse;

logic means receiving said output pulses from both said pulse generators and passing said pulses when output pulses from both pulse generators occur at substantially the same time;

a first output receiving the output pulses from said logic means for coupling those pulses to a processor;

an integrator connected to said first input for integrating said alternating signal and producing a signal representing the resulting integral;

an absolute value circuit receiving the integral signal from said integrator and producing an output signal representing the absolute value of that integral;

a second output receiving the absolute-value integral signal for coupling that signal to the processor;

a second input for receiving a signal from a ground-fault sensor coupled to said power line;

an amplifier connected to said second input for amplifying the ground-fault signal from the ground-fault sensor;

an absolute value circuit receiving the amplified ground-fault signal and producing an output signal representing the absolute value of the amplified ground-fault signal; and

a third output receiving the absolute-value ground-fault signal for coupling that signal to the processor;

a fourth input for receiving a test signal, an amplifier for adjusting the amplitude of said test signal, and a fourth output receiving the amplifier output for coupling the test signal to said arcing-fault sensor;

at least one power-line input for receiving the power line signal, signal conditioning means for adjusting at least the amplitude of the power line signal, and a power-line output receiving the adjusted power line signal for coupling that signal to the processor, and

a watch-dog circuit for receiving a watch-dog signal output from the processor, determining from said watch-dog signal whether the processor is active, and producing a trip signal if it is determined that the processor is not active.

14. A method for detecting faults in an electrical power line using a circuit and a processor-controlled device connected to at least one electrical power line so that the combination of the circuit and the processor-controlled device can detect faults in the power line, said method comprising, at said circuit:

receiving an alternating signal from an arcing-fault sensor coupled to said power line;

passing those components of said alternating signal within a prescribed frequency band;

comparing those components of said alternating signal within said prescribed frequency band with a predetermined threshold and producing an output signal when the predetermined threshold is exceeded;

producing an output pulse corresponding to the output signal;

coupling the output pulses to a processor;

integrating said alternating signal and producing a signal representing the resulting integral;

producing an output signal representing the absolute value of that integral; and

coupling the output signal to the processor.

15. The method of claim 14 which includes:

receiving a signal from a ground-fault sensor coupled to said power line;

amplifying the ground-fault signal from the ground-fault sensor;

producing an output signal representing the absolute value of the amplified ground-fault signal; and

coupling the absolute-value ground-fault signal to the processor.

16. The method of claim 14 which includes:

passing those components of said alternating signal within a second prescribed frequency band;

comparing the components of said alternating signal within said second prescribed frequency band with a second predetermined threshold and producing a second output signal when the second predetermined threshold is exceeded;

receiving the second output signal and producing a corresponding second output pulse;

receiving said output pulses and said second output pulses and producing a further output pulse when both output pulses occur at substantially the same time; and

receiving the further output pulses and coupling those pulses to the processor.

17. The method of claim 14 which includes receiving a test signal, adjusting the amplitude of said test signal, and coupling the amplitude adjusted test signal to said arcing-fault sensor.

18. The method of claim 14 which includes receiving a power line signal, adjusting at least the amplitude of the power line signal, and coupling the adjusted power line signal to the processor.

19. The method of claim 14 which includes receiving a watch-dog signal output from the processor, determining from said watch-dog signal whether the processor is active, and producing a trip signal if it is determined that the processor is not active.