Voltage detection circuit power-on/off reset circuit and semiconductor device

• US 6,246,624 B1
• Filed: 11/24/1998
• Issued: 06/12/2001
• Est. Priority Date: 08/21/1995
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Hirano, Hiroshige, Sumi, Tatsumi, Asari, Kouji
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/198,726
• Time in Patent Office: 931 Days
• Field of Search: 365/226, 365/185.18, 365/189.07, 365/233
• US Class Current: 365/226
• CPC Class Codes: G01R 19/0084 measuring voltage only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G01R 19/155 Indicating the presence of voltage
• CPC Class Codes: G01R 19/16538 in AC or DC supplies G01R19/16519 and G01R19/16528 take precedence
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Claims

1. A power-on/off reset circuit comprising:

a voltage detection circuit which detects a first voltage and outputs a first signal, and,

a control signal generation circuit which generates a control signal based on a reference clocking signal and the first signal;

wherein (a) when a power-supply voltage is higher than the first voltage, the control signal is generated according to the reference clocking signal, and when the power-supply voltage is equal to or lower than the first voltage while the control signal is generated, the generating of the control signal is continued for a predetermined duration and thereafter is ended, and (b) when the power-supply voltage is lower than the first voltage, the control signal is not newly generated regardless of the reference clocking signal.

2. A semiconductor device comprising:

a power-on/off reset circuit which includes

(a) a voltage detection circuit which detects a first voltage and outputs a first signal, and

(b) a control signal generation circuit which generates a control signal based on a reference clocking signal and the first signal,

wherein when a power-supply voltage is lower than the first voltage, the control signal is not newly generated regardless the reference clocking signal; and

a first circuit which executes a series of operational sequences in accordance with the control signal,

wherein the power-on/off reset circuit prevent a new operational sequence from starting in the first circuit when the power-supply voltage is equal to or lower than the first voltage.

4. A semiconductor device according to claim 2 or 3, wherein said first circuit is a non-volatile memory.

3. A semiconductor device comprising:

a power-on/off reset circuit which includes

(a) a voltage detection circuit which detects a first voltage and outputs a first signal, and

(b) a control signal generation circuit which generates a control signal based on a reference clocking signal and the first signal,

wherein when a power-supply voltage is higher than the first voltage, the control signal is generated according to the reference clocking signal, and when a power-supply voltage is equal to or lower than the first voltage while the control signal is generated, the generating of the control signal is continued for a predetermined duration and thereafter is ended; and

a first circuit which executes a series of operational sequences in accordance with the control signal,

wherein the power-on/off reset circuit prevent the first circuit from being suspended until the series of operational sequences which are already being executed are completed when a voltage of the power-supply voltage which is higher than the first voltage changes into a voltage which is equal to or lower than the first voltage.